1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 	 * BIT(27) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
89 	 * BIT(25) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
149 	 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.  in omap4_secondary_init()
150 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA  in omap4_secondary_init()
151 	 * init and for CPU1, a secure PPA API provided. CPU0 must be ON  in omap4_secondary_init()
152 	 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.  in omap4_secondary_init()
153 	 * OMAP443X GP devices- SMP bit isn't accessible.  in omap4_secondary_init()
154 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.  in omap4_secondary_init()
201 	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to  in omap4_boot_secondary()
204 	 * More details can be found in OMAP4430 TRM - Version J  in omap4_boot_secondary()
206 	 *	4.3.4.2 Power States of CPU0 and CPU1  in omap4_boot_secondary()
214 		 * bit 1 == Non-Secure Enable  in omap4_boot_secondary()
215 		 * The Non-Secure banked register has not changed  in omap4_boot_secondary()
216 		 * Because the ROM Code is based on the r1pX GIC, the CPU1  in omap4_boot_secondary()
217 		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.  in omap4_boot_secondary()
219 		 * 1) Before doing the CPU1 wakeup, CPU0 must disable  in omap4_boot_secondary()
221 		 * 2) CPU1 must re-enable the GIC distributor on  in omap4_boot_secondary()
256  * Initialise the CPU possible map early - this describes the CPUs
289  * For now, just make sure the start-up address is not within the booting
293 static bool __init omap4_smp_cpu1_startup_valid(unsigned long addr)  in omap4_smp_cpu1_startup_valid()  argument
295 	if ((addr >= __pa(PAGE_OFFSET)) && (addr <= __pa(__bss_start)))  in omap4_smp_cpu1_startup_valid()
302  * We may need to reset CPU1 before configuring, otherwise kexec boot can end
303  * up trying to use old kernel startup address or suspend-resume will
304  * occasionally fail to bring up CPU1 on 4430 if CPU1 fails to enter deeper
320 		pr_warn("smp: CPU1 not parked?\n");  in omap4_smp_maybe_reset_cpu1()
333 	 * If omap4 or 5 has NS_PA_ADDR configured, CPU1 may be in a  in omap4_smp_maybe_reset_cpu1()
344 	if (!needs_reset || !c->cpu1_rstctrl_va)  in omap4_smp_maybe_reset_cpu1()
347 	pr_info("smp: CPU1 parked within kernel, needs reset (0x%lx 0x%lx)\n",  in omap4_smp_maybe_reset_cpu1()
350 	writel_relaxed(1, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
351 	readl_relaxed(c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
352 	writel_relaxed(0, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
372 	cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;  in omap4_smp_prepare_cpus()
373 	cfg.startup_addr = c->startup_addr;  in omap4_smp_prepare_cpus()
397 	 * AuxCoreBoot1 where ROM code will jump and start executing  in omap4_smp_prepare_cpus()