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/linux-6.14.4/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
12 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
15 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
18 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side",
30 "BriefDescription": "Duration of a translation table walk requested by the instruction side"
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/snowridgex/
Dvirtual-memory.json23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
41 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
50 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
59 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
84 …e number of page walks completed due to stores whose address translations missed in all Translatio…
93 …e number of page walks completed due to stores whose address translations missed in all Translatio…
102 …e number of page walks completed due to stores whose address translations missed in all Translatio…
111 …e number of page walks completed due to stores whose address translations missed in all Translatio…
120 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/elkhartlake/
Dvirtual-memory.json23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
41 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
50 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
59 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
84 …e number of page walks completed due to stores whose address translations missed in all Translatio…
93 …e number of page walks completed due to stores whose address translations missed in all Translatio…
102 …e number of page walks completed due to stores whose address translations missed in all Translatio…
111 …e number of page walks completed due to stores whose address translations missed in all Translatio…
120 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
/linux-6.14.4/Documentation/admin-guide/RAS/
Daddress-translation.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Address translation
7 -------
9 Zen-based AMD systems include a Data Fabric that manages the layout of
12 These devices may provide a "normalized", i.e. device physical, address
14 a system physical address for the kernel to action on the memory.
16 AMD Address Translation Library (CONFIG_AMD_ATL) provides translation for
19 Glossary of acronyms used in address translation for Zen-based systems
22 * COD = Cluster-on-Die
/linux-6.14.4/drivers/of/
Dfdt_address.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FDT Address translation based on u-boot fdt_support.c which in turn was
4 * based on the kernel unflattened DT address translation code.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
41 prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); in fdt_bus_default_count_cells()
45 *addrc = -1; in fdt_bus_default_count_cells()
49 prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); in fdt_bus_default_count_cells()
53 *sizec = -1; in fdt_bus_default_count_cells()
71 return da - cp; in fdt_bus_default_map()
80 addr[na - 2] = cpu_to_fdt32(a >> 32); in fdt_bus_default_translate()
[all …]
/linux-6.14.4/drivers/iommu/riscv/
Diommu-bits.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0
10 * Published at https://github.com/riscv-non-isa/riscv-iommu
67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
69 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt
86 /* 5.5 Device-directory-table pointer (64bits) */
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Driscv,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V IOMMU Architecture Implementation
10 - Tomasz Jeznach <[email protected]>
13 The RISC-V IOMMU provides memory address translation and isolation for
14 input and output devices, supporting per-device translation context,
15 shared process address spaces including the ATS and PRI components of
16 the PCIe specification, two stage address translation and MSI remapping.
17 It supports identical translation table format to the RISC-V address
[all …]
Diommu.txt10 * Remap address space to allow devices to access physical memory ranges that
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
20 address regions.
22 * Provide address space isolation between multiple contexts.
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
15 controller registers provide the control for the translation from the offset
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
21 - Masahiro Yamada <[email protected]>
[all …]
/linux-6.14.4/drivers/ras/amd/atl/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # AMD Address Translation Library Kconfig
11 tristate "AMD Address Translation Library"
17 This library includes support for implementation-specific
18 address translation procedures needed for various error
21 Enable this option if using DRAM ECC on Zen-based systems
22 and OS-based error handling.
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AMD Address Translation Library
5 * core.c : Module init and base translation functions
25 dram_limit_addr = FIELD_GET(DF4_DRAM_LIMIT_ADDR, ctx->map.limit); in addr_over_limit()
27 dram_limit_addr = FIELD_GET(DF2_DRAM_LIMIT_ADDR, ctx->map.limit); in addr_over_limit()
30 dram_limit_addr |= GENMASK(DF_DRAM_BASE_LIMIT_LSB - 1, 0); in addr_over_limit()
32 /* Is calculated system address above DRAM limit address? */ in addr_over_limit()
33 if (ctx->ret_addr > dram_limit_addr) { in addr_over_limit()
34 atl_debug(ctx, "Calculated address (0x%016llx) > DRAM limit (0x%016llx)", in addr_over_limit()
35 ctx->ret_addr, dram_limit_addr); in addr_over_limit()
[all …]
/linux-6.14.4/arch/arm64/mm/
Dfault.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
21 #include <linux/page-flags.h>
37 #include <asm/debug-monitors.h>
116 esr_to_fault_info(esr)->name); in mem_abort_decode()
126 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
128 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
142 mm = current->active_mm; in show_pte()
144 pr_alert("[%016lx] user address but active_mm is swapper\n", in show_pte()
152 pr_alert("[%016lx] address between user and kernel address ranges\n", in show_pte()
[all …]
/linux-6.14.4/tools/perf/pmu-events/arch/x86/grandridge/
Dvirtual-memory.json23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
41 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
66 …e number of page walks completed due to stores whose address translations missed in all Translatio…
75 …e number of page walks completed due to stores whose address translations missed in all Translatio…
84 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
109 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
118 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
127 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
136 …k start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walk…
/linux-6.14.4/tools/perf/pmu-events/arch/x86/sierraforest/
Dvirtual-memory.json23 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
32 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
41 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
66 …e number of page walks completed due to stores whose address translations missed in all Translatio…
75 …e number of page walks completed due to stores whose address translations missed in all Translatio…
84 …e walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
109 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
118 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
127 …age walks completed due to instruction fetches whose address translations missed in all Translatio…
136 …k start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walk…
/linux-6.14.4/Documentation/scsi/
Daha152x.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
8 Copyright |copy| 1993-1999 Jürgen Fischer <[email protected]>
14 bottom-half handler complete()).
26 IOPORT base io address (0x340/0x140)
27 IRQ interrupt level (9-12; default 11)
28 SCSI_ID scsi id of controller (0-7; default 7)
33 EXT_TRANS: enable extended translation (0/1: default 0 [off])
42 - DAUTOCONF
43 use configuration the controller reports (AHA-152x only)
[all …]
/linux-6.14.4/Documentation/virt/kvm/x86/
Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
[all …]
/linux-6.14.4/Documentation/arch/arm64/
Dtagged-pointers.rst10 addresses in the AArch64 translation system and their potential uses
13 The kernel configures the translation tables so that translations made
15 the virtual address ignored by the translation hardware. This frees up
20 --------------------------------------
23 an address tag of 0x00, unless the application enables the AArch64
24 Tagged Address ABI explicitly
25 (Documentation/arch/arm64/tagged-address-abi.rst).
29 - pointer arguments to system calls, including pointers in structures
32 - the stack pointer (sp), e.g. when interpreting it to deliver a
35 - the frame pointer (x29) and frame records, e.g. when interpreting
[all …]
Dmemory.rst8 Linux kernel. The architecture allows up to 4 levels of translation
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
15 virtual address, are used but the memory layout is the same.
17 ARMv8.2 adds optional support for Large Virtual Address space. This is
19 number of descriptors in the first level of translation.
21 TTBRx selection is given by bit 55 of the virtual address. The
23 contains only user (non-global) mappings. The swapper_pg_dir address is
36 52-bit VA support in the kernel
[all …]
/linux-6.14.4/drivers/acpi/acpica/
Drsdumpinfo.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: rsdumpinfo - Tables used to display resource descriptors.
59 "Start-Dependent-Functions", NULL},
70 "End-Dependent-Functions", NULL}
75 {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(io.io_decode), "Address Decoding",
77 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.minimum), "Address Minimum", NULL},
78 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.maximum), "Address Maximum", NULL},
80 {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(io.address_length), "Address Length",
87 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_io.address), "Address", NULL},
89 "Address Length", NULL}
[all …]
Drsaddr.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: rsaddr - Address resource descriptors (16/32/64)
17 * acpi_rs_convert_address16 - All WORD (16-bit) address resources
29 /* Resource Type, General Flags, and Type-Specific Flags */
35 * Address Granularity
36 * Address Range Minimum
37 * Address Range Maximum
38 * Address Translation Offset
39 * Address Length
41 {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.address16.address.granularity),
[all …]
/linux-6.14.4/Documentation/driver-api/
Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
8 registers and memory translation windows, as well as non common features like
9 scratchpad and message registers. Scratchpad registers are read-and-writable
11 exchange a small amount of information at a fixed address. Message registers can
36 ----------------------------------------
42 inbound translation configured on the local ntb port and outbound translation
46 Inbound translation:
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/
Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
[all …]
/linux-6.14.4/drivers/dma/fsl-dpaa2-qdma/
Ddpaa2-qdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 u32 rbpcmd; /* Route-by-port command */
38 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
39 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
54 #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */
55 #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */
56 /* Flow Context: 49bit physical address */
58 #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */
63 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
64 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
[all …]
/linux-6.14.4/arch/arm64/kvm/
Dstacktrace.c1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * 1) Non-protected nVHE mode - the host can directly access the
12 * 2) pKVM (protected nVHE) mode - the host cannot directly access
29 unsigned long low = (unsigned long)stacktrace_info->overflow_stack_base; in stackinfo_get_overflow()
53 unsigned long low = (unsigned long)stacktrace_info->stack_base; in stackinfo_get_hyp()
74 * kvm_nvhe_stack_kern_va - Convert KVM nVHE HYP stack addresses to a kernel VAs
77 * allow for guard pages below the stack. Consequently, the fixed offset address
78 * translation macros won't work here.
103 *addr = *addr - stack_hyp.low + stack_kern.low; in kvm_nvhe_stack_kern_va()
108 * Convert a KVN nVHE HYP frame record address to a kernel VA
[all …]
/linux-6.14.4/Documentation/admin-guide/mm/
Dconcepts.rst7 systems from MMU-less microcontrollers to supercomputers. The memory
12 address to a physical address.
23 address ranges. Besides, different CPU architectures, and even
25 of how these address ranges are defined.
36 address. When the CPU decodes an instruction that reads (or
38 address encoded in that instruction to a `physical` address that the
49 translation from a virtual address used by programs to the physical
50 memory address. The page tables are organized hierarchically.
56 register. When the CPU performs the address translation, it uses this
58 virtual address are used to index an entry in the top level page
[all …]

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