Lines Matching +full:address +full:- +full:translation

7 systems from MMU-less microcontrollers to supercomputers. The memory
12 address to a physical address.
23 address ranges. Besides, different CPU architectures, and even
25 of how these address ranges are defined.
36 address. When the CPU decodes an instruction that reads (or
38 address encoded in that instruction to a `physical` address that the
49 translation from a virtual address used by programs to the physical
50 memory address. The page tables are organized hierarchically.
56 register. When the CPU performs the address translation, it uses this
58 virtual address are used to index an entry in the top level page
60 hierarchy with the next bits of the virtual address as the index to
61 that level page table. The lowest bits in the virtual address define
67 The address translation requires several memory accesses and memory
69 processor cycles on the address translation, CPUs maintain a cache of
70 such translations called Translation Lookaside Buffer (or
80 improves TLB hit-rate and thus improves overall system performance.
87 Documentation/admin-guide/mm/hugetlbpage.rst.
94 name. See Documentation/admin-guide/mm/transhuge.rst for more details
108 permanently mapped into kernel's address space and ZONE_NORMAL will
118 Many multi-processor machines are NUMA - Non-Uniform Memory Access -
126 Documentation/admin-guide/mm/numa_memory_policy.rst.
173 reclaimed. For instance, in-memory caches of filesystem metadata can
174 be re-read from the storage device and therefore it is possible to
189 more and reaches another threshold - min watermark - an allocation