Lines Matching +full:address +full:- +full:translation
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2022-2024 Rivos Inc.
4 * Copyright © 2023 FORTH-ICS/CARV
5 * Copyright © 2023 RISC-V IOMMU Task Group
7 * RISC-V IOMMU - Register Layout and Data Structures.
9 * Based on the 'RISC-V IOMMU Architecture Specification', Version 1.0
10 * Published at https://github.com/riscv-non-isa/riscv-iommu
67 * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
69 * @RISCV_IOMMU_CAPABILITIES_IGS_WSI: IOMMU supports only Wired-Signaled interrupt
86 /* 5.5 Device-directory-table pointer (64bits) */
93 * enum riscv_iommu_ddtp_modes - IOMMU translation modes
95 * @RISCV_IOMMU_DDTP_IOMMU_MODE_BARE: Pass-through mode
96 * @RISCV_IOMMU_DDTP_IOMMU_MODE_1LVL: One-level DDT
97 * @RISCV_IOMMU_DDTP_IOMMU_MODE_2LVL: Two-level DDT
98 * @RISCV_IOMMU_DDTP_IOMMU_MODE_3LVL: Three-level DDT
223 /* Number of defined performance-monitoring event selectors */
227 * enum riscv_iommu_hpmevent_id - Performance-monitoring event identifier
232 * @RISCV_IOMMU_HPMEVENT_ATS_RQ: ATS translation requests
236 * @RISCV_IOMMU_HPMEVENT_S_VS_WALKS: First-stage page table walks
237 * @RISCV_IOMMU_HPMEVENT_G_WALKS: Second-stage page table walks
253 /* 5.24 Translation request IOVA (64bits) */
257 /* 5.25 Translation request control (64bits) */
267 /* 5.26 Translation request response (64bits) */
300 * Device Directory Table macros for non-leaf nodes
306 * struct riscv_iommu_dc - Device Context
307 * @tc: Translation Control
308 * @iohgatp: I/O Hypervisor guest address translation and protection
310 * @ta: Translation Attributes
313 * @msi_addr_mask: MSI address mask
314 * @msi_addr_pattern: MSI address pattern
334 /* Translation control fields */
348 /* Second-stage (aka G-stage) context fields */
354 * enum riscv_iommu_dc_iohgatp_modes - Guest address translation/protection modes
355 * @RISCV_IOMMU_DC_IOHGATP_MODE_BARE: No translation/protection
356 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4: Sv32x4 (2-bit extension of Sv32), when fctl.GXL == 1
357 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4: Sv39x4 (2-bit extension of Sv39), when fctl.GXL == 0
358 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4: Sv48x4 (2-bit extension of Sv48), when fctl.GXL == 0
359 * @RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4: Sv57x4 (2-bit extension of Sv57), when fctl.GXL == 0
369 /* Translation attributes fields */
372 /* First-stage context fields */
377 * enum riscv_iommu_dc_fsc_atp_modes - First stage address translation/protection modes
378 * @RISCV_IOMMU_DC_FSC_MODE_BARE: No translation/protection
388 * IOSATP controls the first stage address translation (same as the satp register on
389 * the RISC-V MMU), and PDTP holds the process directory table, used to select a
410 /* MSI address mask */
413 /* MSI address pattern */
417 * struct riscv_iommu_pc - Process Context
418 * @ta: Translation Attributes
429 /* Translation attributes fields */
440 * Chapter 3: In-memory queue interface
444 * struct riscv_iommu_command - Generic IOMMU command structure
451 * function invoked by that command, and the rest is opcode-specific.
465 /* 3.1.1 IOMMU Page-table cache invalidation */
475 /* dword1[61:10] is the 4K-aligned page address */
487 /* dword1 is the address, word-size aligned and shifted to the right by two bits. */
513 /* Bits 1 - 10 are zeroed */
518 /* Bits 0 - 31 are zeroed */
520 /* Bits 41 - 43 are zeroed */
525 * struct riscv_iommu_fq_record - Fault/Event Queue Record
528 * @iotval: Transaction-type/cause specific format
535 * fault/event-specific information. For more details see section
554 * enum riscv_iommu_fq_causes - Fault/event cause values
556 * @RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED: Read address misaligned
558 * @RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED: Write/AMO address misaligned
586 * Values are on table 11 of the spec, encodings 275 - 2047 are reserved for standard
587 * use, and 2048 - 4095 for custom use.
625 * @RISCV_IOMMU_FQ_TTYP_UADDR_INST_FETCH: Instruction fetch from untranslated address
626 * @RISCV_IOMMU_FQ_TTYP_UADDR_RD: Read from untranslated address
627 * @RISCV_IOMMU_FQ_TTYP_UADDR_WR: Write/AMO to untranslated address
628 * @RISCV_IOMMU_FQ_TTYP_TADDR_INST_FETCH: Instruction fetch from translated address
629 * @RISCV_IOMMU_FQ_TTYP_TADDR_RD: Read from translated address
630 * @RISCV_IOMMU_FQ_TTYP_TADDR_WR: Write/AMO to translated address
631 * @RISCV_IOMMU_FQ_TTYP_PCIE_ATS_REQ: PCIe ATS translation request
634 * Values are on table 12 of the spec, type 4 and 10 - 31 are reserved for standard use
635 * and 31 - 63 for custom use.
650 * struct riscv_iommu_pq_record - PCIe Page Request record
652 * @payload: Holds the page address, request group and permission bits
677 * struct riscv_iommu_msipte - MSI Page Table Entry
679 * @mrif_info: Memory-resident interrupt file info
683 * by translating the MSI address, either to a guest interrupt file
685 * is an array of MSI PTEs, not a multi-level pt, each entry
689 * be used by software, any other reserved fields on pte must be zeroed-out
713 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOTINVAL_OPCODE) | in riscv_iommu_cmd_inval_vma()
715 cmd->dword1 = 0; in riscv_iommu_cmd_inval_vma()
721 cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, phys_to_pfn(addr)); in riscv_iommu_cmd_inval_set_addr()
722 cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV; in riscv_iommu_cmd_inval_set_addr()
728 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_PSCID, pscid) | in riscv_iommu_cmd_inval_set_pscid()
735 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_GSCID, gscid) | in riscv_iommu_cmd_inval_set_gscid()
741 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence()
744 cmd->dword1 = 0; in riscv_iommu_cmd_iofence()
750 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IOFENCE_OPCODE) | in riscv_iommu_cmd_iofence_set_av()
754 cmd->dword1 = addr >> 2; in riscv_iommu_cmd_iofence_set_av()
759 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_ddt()
761 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_ddt()
766 cmd->dword0 = FIELD_PREP(RISCV_IOMMU_CMD_OPCODE, RISCV_IOMMU_CMD_IODIR_OPCODE) | in riscv_iommu_cmd_iodir_inval_pdt()
768 cmd->dword1 = 0; in riscv_iommu_cmd_iodir_inval_pdt()
774 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_DID, devid) | in riscv_iommu_cmd_iodir_set_did()
781 cmd->dword0 |= FIELD_PREP(RISCV_IOMMU_CMD_IODIR_PID, pasid); in riscv_iommu_cmd_iodir_set_pid()