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123

/linux-6.14.4/drivers/clk/samsung/
Dclk-exynos990.c436 PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
438 PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
440 PLL(pll_0718x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
442 PLL(pll_0718x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
444 PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
446 PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
448 PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
453 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
454 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
455 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
[all …]
Dclk-exynos8895.c502 PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
505 PLL(pll_1051x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
508 PLL(pll_1052x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
511 PLL(pll_1052x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
514 PLL(pll_1052x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
520 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
521 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
522 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
523 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
524 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
[all …]
Dclk-exynos7885.c157 PLL(pll_1417x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
160 PLL(pll_1417x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
166 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
167 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
179 PNAME(mout_peri_spi0_p) = { "oscclk", "dout_shared0_div4" };
180 PNAME(mout_peri_spi1_p) = { "oscclk", "dout_shared0_div4" };
181 PNAME(mout_peri_uart0_p) = { "oscclk", "dout_shared0_div4" };
182 PNAME(mout_peri_uart1_p) = { "oscclk", "dout_shared0_div4" };
183 PNAME(mout_peri_uart2_p) = { "oscclk", "dout_shared0_div4" };
184 PNAME(mout_peri_usi0_p) = { "oscclk", "dout_shared0_div4" };
[all …]
Dclk-exynosautov920.c328 PLL(pll_531x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
330 PLL(pll_531x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
332 PLL(pll_531x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
334 PLL(pll_531x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
336 PLL(pll_531x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
338 PLL(pll_531x, FOUT_SHARED5_PLL, "fout_shared5_pll", "oscclk",
340 PLL(pll_531x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
345 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
346 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
347 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
[all …]
Dclk-gs101.c638 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
641 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
644 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
647 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
650 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
656 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
657 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
658 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
659 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
660 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" };
[all …]
Dclk-exynos850.c234 PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
237 PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
240 PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
245 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
246 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
247 PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
258 PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
261 "oscclk", "oscclk" };
277 PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
280 "oscclk", "oscclk" };
[all …]
Dclk-exynosautov9.c354 PLL(pll_0822x, FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
356 PLL(pll_0822x, FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
358 PLL(pll_0822x, FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
360 PLL(pll_0822x, FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
362 PLL(pll_0822x, FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
367 PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
368 PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
369 PNAME(mout_shared2_pll_p) = { "oscclk", "fout_shared2_pll" };
370 PNAME(mout_shared3_pll_p) = { "oscclk", "fout_shared3_pll" };
371 PNAME(mout_shared4_pll_p) = { "oscclk", "fout_shared4_pll" };
[all …]
Dclk-exynos5433.c213 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
214 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
215 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
216 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
217 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
218 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
219 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
220 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
251 "oscclk", "ioclk_spdif_extclk", };
252 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml18 - "oscclk" - PLL input clock from XXTI
106 - const: oscclk
126 - const: oscclk
143 - const: oscclk
161 - const: oscclk
187 - const: oscclk
206 - const: oscclk
231 - const: oscclk
283 - const: oscclk
301 - const: oscclk
[all …]
Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
77 - const: oscclk
94 - const: oscclk
112 - const: oscclk
130 - const: oscclk
151 - const: oscclk
173 - const: oscclk
193 - const: oscclk
212 - const: oscclk
230 - const: oscclk
[all …]
Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
21 The external OSCCLK must be defined as fixed-rate clock in dts.
75 - const: oscclk
92 - const: oscclk
110 - const: oscclk
128 - const: oscclk
147 - const: oscclk
168 - const: oscclk
190 - const: oscclk
211 - const: oscclk
[all …]
Dsamsung,exynos8895-clock.yaml18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
81 - const: oscclk
106 - const: oscclk
132 - const: oscclk
169 - const: oscclk
201 - const: oscclk
218 - const: oscclk
231 clocks = <&oscclk>,
236 clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
Dsamsung,exynosautov920-clock.yaml19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
20 The external OSCCLK must be defined as fixed-rate clock in dts.
70 - const: oscclk
90 - const: oscclk
110 - const: oscclk
130 - const: oscclk
157 clock-names = "oscclk",
Dsamsung,exynos7885-clock.yaml20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
68 - const: oscclk
87 - const: oscclk
111 - const: oscclk
141 - const: oscclk
171 clocks = <&oscclk>,
181 clock-names = "oscclk",
Dgoogle,gs101-clock.yaml16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
75 - const: oscclk
95 - const: oscclk
120 - const: oscclk
162 - const: oscclk
178 clock-names = "oscclk";
Dsamsung,exynos990-clock.yaml18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
76 - const: oscclk
96 - const: oscclk
109 clocks = <&oscclk>,
114 clock-names = "oscclk",
/linux-6.14.4/arch/arm64/boot/dts/exynos/
Dexynos850.dtsi49 oscclk: clock-oscclk { label
51 clock-output-names = "oscclk";
187 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>;
231 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>;
242 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>;
254 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
257 clock-names = "oscclk", "dout_peri_bus",
266 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
268 clock-names = "oscclk", "dout_cpucl1_switch",
277 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
[all …]
Dexynos8895.dtsi146 oscclk: osc-clock { label
149 clock-output-names = "oscclk";
177 clocks = <&oscclk>,
179 clock-names = "oscclk", "bus";
186 clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
220 clocks = <&oscclk>,
227 clock-names = "oscclk", "bus", "uart", "usi0",
254 clocks = <&oscclk>,
270 clock-names = "oscclk", "bus", "speedy", "cam0",
373 clocks = <&oscclk>,
[all …]
Dexynos7885.dtsi161 oscclk: osc-clock { label
164 clock-output-names = "oscclk";
198 clocks = <&oscclk>,
208 clock-names = "oscclk",
225 clocks = <&oscclk>,
229 clock-names = "oscclk",
240 clocks = <&oscclk>;
241 clock-names = "oscclk";
249 clocks = <&oscclk>,
255 clock-names = "oscclk",
Dexynos990.dtsi160 oscclk: clock-osc { label
163 clock-output-names = "oscclk";
215 clocks = <&oscclk>,
220 clock-names = "oscclk",
279 clocks = <&oscclk>;
280 clock-names = "oscclk";
Dexynosautov920.dtsi39 clock-output-names = "oscclk";
182 clock-names = "oscclk",
287 clock-names = "oscclk",
352 clock-names = "oscclk",
375 clock-names = "oscclk";
400 clock-names = "oscclk",
419 clock-names = "oscclk",
Dexynos5433.dtsi47 clock-output-names = "oscclk";
374 clock-names = "oscclk",
389 clock-names = "oscclk";
398 clock-names = "oscclk",
421 clock-names = "oscclk",
448 clock-names = "oscclk",
462 clock-names = "oscclk",
487 clock-names = "oscclk", "fout_aud_pll";
515 clock-names = "oscclk", "aclk_bus2_400";
524 clock-names = "oscclk", "aclk_g3d_400";
[all …]
Dexynos850-e850-96.dts171 clocks = <&oscclk>, <&rtcclk>,
175 clock-names = "oscclk", "rtcclk", "dout_hsi_bus",
199 &oscclk {
/linux-6.14.4/drivers/watchdog/
Drzv2h_wdt.c51 struct clk *oscclk; member
104 * - CKS[7:4] - Clock Division Ratio Select - 0101b: oscclk/256 in rzv2h_wdt_start()
153 ret = clk_enable(priv->oscclk); in rzv2h_wdt_restart()
161 clk_disable(priv->oscclk); in rzv2h_wdt_restart()
182 * - CKS[7:4] - Clock Division Ratio Select - 0000b: oscclk/1 in rzv2h_wdt_restart()
224 priv->oscclk = devm_clk_get_prepared(dev, "oscclk"); in rzv2h_wdt_probe()
225 if (IS_ERR(priv->oscclk)) in rzv2h_wdt_probe()
226 return dev_err_probe(dev, PTR_ERR(priv->oscclk), "no oscclk"); in rzv2h_wdt_probe()
234 clk_get_rate(priv->oscclk); in rzv2h_wdt_probe()
/linux-6.14.4/Documentation/devicetree/bindings/display/samsung/
Dsamsung,exynos-hdmi.yaml121 - description: MUX used to switch between oscclk and tmds_clko,
124 - description: MUX used to switch between oscclk and pixel_clko,
139 - const: oscclk
195 "oscclk",

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