1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2024 Igor Belwon <[email protected]>
4 *
5 * Common Clock Framework support for Exynos990.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <dt-bindings/clock/samsung,exynos990.h>
14
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
17 #include "clk-pll.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1)
21 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1)
22
23 /* ---- CMU_TOP ------------------------------------------------------------- */
24
25 /* Register Offset definitions for CMU_TOP (0x1a330000) */
26 #define PLL_LOCKTIME_PLL_G3D 0x0000
27 #define PLL_LOCKTIME_PLL_MMC 0x0004
28 #define PLL_LOCKTIME_PLL_SHARED0 0x0008
29 #define PLL_LOCKTIME_PLL_SHARED1 0x000c
30 #define PLL_LOCKTIME_PLL_SHARED2 0x0010
31 #define PLL_LOCKTIME_PLL_SHARED3 0x0014
32 #define PLL_LOCKTIME_PLL_SHARED4 0x0018
33 #define PLL_CON0_PLL_G3D 0x0100
34 #define PLL_CON3_PLL_G3D 0x010c
35 #define PLL_CON0_PLL_MMC 0x0140
36 #define PLL_CON3_PLL_MMC 0x014c
37 #define PLL_CON0_PLL_SHARED0 0x0180
38 #define PLL_CON3_PLL_SHARED0 0x018c
39 #define PLL_CON0_PLL_SHARED1 0x01c0
40 #define PLL_CON3_PLL_SHARED1 0x01cc
41 #define PLL_CON0_PLL_SHARED2 0x0200
42 #define PLL_CON3_PLL_SHARED2 0x020c
43 #define PLL_CON0_PLL_SHARED3 0x0240
44 #define PLL_CON3_PLL_SHARED3 0x024c
45 #define PLL_CON0_PLL_SHARED4 0x0280
46 #define PLL_CON3_PLL_SHARED4 0x028c
47 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
48 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
49 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
50 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1010
51 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS 0x1014
52 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1018
53 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x101c
54 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1020
55 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1024
56 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1028
57 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x102c
58 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
59 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1034
60 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS 0x1038
61 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x103c
62 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1040
63 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP 0x1044
64 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
65 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
66 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU 0x1050
67 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUS 0x1054
68 #define CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM 0x1058
69 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x105c
70 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1060
71 #define CLK_CON_MUX_MUX_CLKCMU_DPU_ALT 0x1064
72 #define CLK_CON_MUX_MUX_CLKCMU_DSP_BUS 0x1068
73 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x106c
74 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1070
75 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1074
76 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1078
77 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x107c
78 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1080
79 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG 0x1084
80 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1088
81 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD 0x108c
82 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x1090
83 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD 0x1094
84 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD 0x1098
85 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x109c
86 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a0
87 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10a4
88 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10a8
89 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS 0x10ac
90 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC 0x10b0
91 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU 0x10b4
92 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0 0x10b8
93 #define CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD 0x10bc
94 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c0
95 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c4
96 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10c8
97 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10cc
98 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10d0
99 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10d4
100 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10d8
101 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10dc
102 #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
103 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
104 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
105 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
106 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
107 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
108 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x180c
109 #define CLK_CON_DIV_CLKCMU_BUS1_SSS 0x1810
110 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1814
111 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1818
112 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x181c
113 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x1820
114 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1824
115 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1828
116 #define CLK_CON_DIV_CLKCMU_CMU_BOOST 0x182c
117 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
118 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS 0x1834
119 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
120 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
121 #define CLK_CON_DIV_CLKCMU_CPUCL2_BUSP 0x1840
122 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1844
123 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1848
124 #define CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU 0x184c
125 #define CLK_CON_DIV_CLKCMU_DNC_BUS 0x1850
126 #define CLK_CON_DIV_CLKCMU_DNC_BUSM 0x1854
127 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x1858
128 #define CLK_CON_DIV_CLKCMU_DSP_BUS 0x185c
129 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1860
130 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1864
131 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1868
132 #define CLK_CON_DIV_CLKCMU_HPM 0x186c
133 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1870
134 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1874
135 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1878
136 #define CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG 0x187c
137 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1880
138 #define CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD 0x1884
139 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1888
140 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD 0x188c
141 #define CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD 0x1890
142 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1894
143 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x1898
144 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x189c
145 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18a0
146 #define CLK_CON_DIV_CLKCMU_MCSC_BUS 0x18a4
147 #define CLK_CON_DIV_CLKCMU_MCSC_GDC 0x18a8
148 #define CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU 0x18ac
149 #define CLK_CON_DIV_CLKCMU_MFC0_MFC0 0x18b0
150 #define CLK_CON_DIV_CLKCMU_MFC0_WFD 0x18b4
151 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18b8
152 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x18bc
153 #define CLK_CON_DIV_CLKCMU_OTP 0x18c0
154 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18c4
155 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18c8
156 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18cc
157 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18d0
158 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18d4
159 #define CLK_CON_DIV_CLKCMU_SSP_BUS 0x18d8
160 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18dc
161 #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
162 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
163 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
164 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
165 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
166 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
167 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1900
168 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1904
169 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1908
170 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x190c
171 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x1910
172 #define CLK_CON_DIV_PLL_SHARED4_DIV3 0x1914
173 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x1918
174 #define CLK_CON_GAT_CLKCMU_G3D_BUS 0x2000
175 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2004
176 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
177 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x200c
178 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2010
179 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x2014
180 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS 0x2018
181 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x201c
182 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2020
183 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2024
184 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2028
185 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x202c
186 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2030
187 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2034
188 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x2038
189 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x203c
190 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2040
191 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP 0x2044
192 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2048
193 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x204c
194 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU 0x2050
195 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUS 0x2054
196 #define CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM 0x2058
197 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x205c
198 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x2060
199 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2064
200 #define CLK_CON_GAT_GATE_CLKCMU_DSP_BUS 0x2068
201 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x206c
202 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2070
203 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2074
204 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x2078
205 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x207c
206 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x2080
207 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x2084
208 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG 0x2088
209 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x208c
210 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD 0x2090
211 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x2094
212 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD 0x2098
213 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD 0x209c
214 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20a0
215 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20a4
216 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20a8
217 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20ac
218 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS 0x20b0
219 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC 0x20b4
220 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0 0x20bc
221 #define CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD 0x20c0
222 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c4
223 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c8
224 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20cc
225 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20d0
226 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d4
227 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d8
228 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20dc
229 #define CLK_CON_GAT_GATE_CLKCMU_SSP_BUS 0x20e0
230 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x20e4
231 #define CLK_CON_GAT_GATE_CLKCMU_VRA_BUS 0x20e8
232
233 static const unsigned long top_clk_regs[] __initconst = {
234 PLL_LOCKTIME_PLL_G3D,
235 PLL_LOCKTIME_PLL_MMC,
236 PLL_LOCKTIME_PLL_SHARED0,
237 PLL_LOCKTIME_PLL_SHARED1,
238 PLL_LOCKTIME_PLL_SHARED2,
239 PLL_LOCKTIME_PLL_SHARED3,
240 PLL_LOCKTIME_PLL_SHARED4,
241 PLL_CON3_PLL_G3D,
242 PLL_CON3_PLL_MMC,
243 PLL_CON3_PLL_SHARED0,
244 PLL_CON3_PLL_SHARED1,
245 PLL_CON3_PLL_SHARED2,
246 PLL_CON3_PLL_SHARED3,
247 PLL_CON3_PLL_SHARED4,
248 CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
249 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
250 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
251 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
252 CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS,
253 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
254 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
255 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
256 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
257 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
258 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
259 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
260 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
261 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
262 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
263 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
264 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
265 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
266 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
267 CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
268 CLK_CON_MUX_MUX_CLKCMU_DNC_BUS,
269 CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM,
270 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
271 CLK_CON_MUX_MUX_CLKCMU_DPU,
272 CLK_CON_MUX_MUX_CLKCMU_DPU_ALT,
273 CLK_CON_MUX_MUX_CLKCMU_DSP_BUS,
274 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
275 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
276 CLK_CON_MUX_MUX_CLKCMU_HPM,
277 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
278 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
279 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
280 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG,
281 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
282 CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
283 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
284 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
285 CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
286 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
287 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
288 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
289 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
290 CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS,
291 CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC,
292 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
293 CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0,
294 CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD,
295 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
296 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
297 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS,
298 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
299 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
300 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
301 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
302 CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS,
303 CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
304 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
305 CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
306 CLK_CON_DIV_CLKCMU_APM_BUS,
307 CLK_CON_DIV_CLKCMU_AUD_CPU,
308 CLK_CON_DIV_CLKCMU_BUS0_BUS,
309 CLK_CON_DIV_CLKCMU_BUS1_BUS,
310 CLK_CON_DIV_CLKCMU_BUS1_SSS,
311 CLK_CON_DIV_CLKCMU_CIS_CLK0,
312 CLK_CON_DIV_CLKCMU_CIS_CLK1,
313 CLK_CON_DIV_CLKCMU_CIS_CLK2,
314 CLK_CON_DIV_CLKCMU_CIS_CLK3,
315 CLK_CON_DIV_CLKCMU_CIS_CLK4,
316 CLK_CON_DIV_CLKCMU_CIS_CLK5,
317 CLK_CON_DIV_CLKCMU_CMU_BOOST,
318 CLK_CON_DIV_CLKCMU_CORE_BUS,
319 CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
320 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
321 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
322 CLK_CON_DIV_CLKCMU_CPUCL2_BUSP,
323 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
324 CLK_CON_DIV_CLKCMU_CSIS_BUS,
325 CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU,
326 CLK_CON_DIV_CLKCMU_DNC_BUS,
327 CLK_CON_DIV_CLKCMU_DNC_BUSM,
328 CLK_CON_DIV_CLKCMU_DNS_BUS,
329 CLK_CON_DIV_CLKCMU_DSP_BUS,
330 CLK_CON_DIV_CLKCMU_G2D_G2D,
331 CLK_CON_DIV_CLKCMU_G2D_MSCL,
332 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
333 CLK_CON_DIV_CLKCMU_HPM,
334 CLK_CON_DIV_CLKCMU_HSI0_BUS,
335 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
336 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
337 CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
338 CLK_CON_DIV_CLKCMU_HSI1_BUS,
339 CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
340 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
341 CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
342 CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
343 CLK_CON_DIV_CLKCMU_HSI2_BUS,
344 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
345 CLK_CON_DIV_CLKCMU_IPP_BUS,
346 CLK_CON_DIV_CLKCMU_ITP_BUS,
347 CLK_CON_DIV_CLKCMU_MCSC_BUS,
348 CLK_CON_DIV_CLKCMU_MCSC_GDC,
349 CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
350 CLK_CON_DIV_CLKCMU_MFC0_MFC0,
351 CLK_CON_DIV_CLKCMU_MFC0_WFD,
352 CLK_CON_DIV_CLKCMU_MIF_BUSP,
353 CLK_CON_DIV_CLKCMU_NPU_BUS,
354 CLK_CON_DIV_CLKCMU_OTP,
355 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
356 CLK_CON_DIV_CLKCMU_PERIC0_IP,
357 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
358 CLK_CON_DIV_CLKCMU_PERIC1_IP,
359 CLK_CON_DIV_CLKCMU_PERIS_BUS,
360 CLK_CON_DIV_CLKCMU_SSP_BUS,
361 CLK_CON_DIV_CLKCMU_TNR_BUS,
362 CLK_CON_DIV_CLKCMU_VRA_BUS,
363 CLK_CON_DIV_DIV_CLKCMU_DPU,
364 CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
365 CLK_CON_DIV_PLL_SHARED0_DIV2,
366 CLK_CON_DIV_PLL_SHARED0_DIV3,
367 CLK_CON_DIV_PLL_SHARED0_DIV4,
368 CLK_CON_DIV_PLL_SHARED1_DIV2,
369 CLK_CON_DIV_PLL_SHARED1_DIV3,
370 CLK_CON_DIV_PLL_SHARED1_DIV4,
371 CLK_CON_DIV_PLL_SHARED2_DIV2,
372 CLK_CON_DIV_PLL_SHARED4_DIV2,
373 CLK_CON_DIV_PLL_SHARED4_DIV3,
374 CLK_CON_DIV_PLL_SHARED4_DIV4,
375 CLK_CON_GAT_CLKCMU_G3D_BUS,
376 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
377 CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
378 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU,
379 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
380 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
381 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS,
382 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
383 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
384 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
385 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
386 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
387 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
388 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
389 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
390 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
391 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
392 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
393 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
394 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
395 CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
396 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS,
397 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM,
398 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
399 CLK_CON_GAT_GATE_CLKCMU_DPU,
400 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
401 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS,
402 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
403 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
404 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
405 CLK_CON_GAT_GATE_CLKCMU_HPM,
406 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
407 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
408 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
409 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
410 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
411 CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
412 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
413 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
414 CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
415 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
416 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
417 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
418 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
419 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS,
420 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC,
421 CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
422 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD,
423 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
424 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS,
425 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
426 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
427 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
428 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
429 CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
430 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS,
431 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
432 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS,
433 };
434
435 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
436 PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
437 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL),
438 PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
439 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1, NULL),
440 PLL(pll_0718x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
441 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2, NULL),
442 PLL(pll_0718x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
443 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL),
444 PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk",
445 PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL),
446 PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
447 PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
448 PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
449 PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL),
450 };
451
452 /* Parent clock list for CMU_TOP muxes*/
453 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
454 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
455 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
456 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
457 PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
458 PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
459 PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
460 PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
461 "dout_cmu_shared2_div2" };
462 PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
463 "fout_shared2_pll",
464 "dout_cmu_shared4_div2",
465 "dout_cmu_shared0_div4" };
466 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
467 "dout_cmu_shared1_div4",
468 "dout_cmu_shared2_div2",
469 "oscclk" };
470 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div4",
471 "dout_cmu_shared1_div4",
472 "dout_cmu_shared2_div2",
473 "oscclk" };
474 PNAME(mout_cmu_bus1_sss_p) = { "dout_cmu_shared0_div4",
475 "dout_cmu_shared1_div4",
476 "dout_cmu_shared2_div2",
477 "oscclk" };
478 PNAME(mout_cmu_cis_clk0_p) = { "oscclk",
479 "dout_cmu_shared2_div2" };
480 PNAME(mout_cmu_cis_clk1_p) = { "oscclk",
481 "dout_cmu_shared2_div2" };
482 PNAME(mout_cmu_cis_clk2_p) = { "oscclk",
483 "dout_cmu_shared2_div2" };
484 PNAME(mout_cmu_cis_clk3_p) = { "oscclk",
485 "dout_cmu_shared2_div2" };
486 PNAME(mout_cmu_cis_clk4_p) = { "oscclk",
487 "dout_cmu_shared2_div2" };
488 PNAME(mout_cmu_cis_clk5_p) = { "oscclk",
489 "dout_cmu_shared2_div2" };
490 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
491 "dout_cmu_shared1_div4",
492 "dout_cmu_shared2_div2",
493 "oscclk" };
494 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
495 "dout_cmu_shared1_div2",
496 "fout_shared2_pll",
497 "dout_cmu_shared0_div3",
498 "dout_cmu_shared1_div3",
499 "dout_cmu_shared0_div4",
500 "fout_shared3_pll", "oscclk" };
501 PNAME(mout_cmu_cpucl0_dbg_bus_p) = { "fout_shared2_pll",
502 "dout_cmu_shared0_div3",
503 "dout_cmu_shared0_div4",
504 "oscclk" };
505 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
506 "dout_cmu_shared0_div2",
507 "fout_shared2_pll",
508 "dout_cmu_shared0_div4" };
509 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
510 "dout_cmu_shared0_div2",
511 "fout_shared2_pll",
512 "dout_cmu_shared0_div4" };
513 PNAME(mout_cmu_cpucl2_busp_p) = { "dout_cmu_shared0_div4",
514 "dout_cmu_shared2_div2" };
515 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared4_pll",
516 "dout_cmu_shared0_div2",
517 "fout_shared2_pll",
518 "dout_cmu_shared0_div4" };
519 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3",
520 "dout_cmu_shared4_div2",
521 "dout_cmu_shared0_div4",
522 "dout_cmu_shared4_div3" };
523 PNAME(mout_cmu_csis_ois_mcu_p) = { "dout_cmu_shared0_div4",
524 "dout_cmu_shared2_div2" };
525 PNAME(mout_cmu_dnc_bus_p) = { "dout_cmu_shared1_div2",
526 "fout_shared2_pll",
527 "dout_cmu_shared4_div2",
528 "dout_cmu_shared0_div4" };
529 PNAME(mout_cmu_dnc_busm_p) = { "dout_cmu_shared0_div4",
530 "dout_cmu_shared1_div4",
531 "dout_cmu_shared2_div2",
532 "dout_cmu_shared4_div4" };
533 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3",
534 "dout_cmu_shared4_div2",
535 "dout_cmu_shared0_div4",
536 "dout_cmu_shared1_div4",
537 "dout_cmu_shared4_div3",
538 "dout_cmu_shared2_div2",
539 "oscclk", "oscclk" };
540 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
541 "dout_cmu_shared0_div4" };
542 PNAME(mout_cmu_dpu_alt_p) = { "dout_cmu_shared4_div2",
543 "dout_cmu_shared4_div3",
544 "dout_cmu_shared2_div2",
545 "oscclk" };
546 PNAME(mout_cmu_dsp_bus_p) = { "dout_cmu_shared0_div2",
547 "dout_cmu_shared1_div2",
548 "fout_shared2_pll",
549 "dout_cmu_shared4_div2",
550 "fout_shared3_pll", "oscclk",
551 "oscclk", "oscclk" };
552 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3",
553 "dout_cmu_shared4_div2",
554 "dout_cmu_shared0_div4",
555 "dout_cmu_shared2_div2" };
556 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
557 "dout_cmu_shared2_div2",
558 "dout_cmu_shared4_div4",
559 "oscclk" };
560 PNAME(mout_cmu_hpm_p) = { "oscclk",
561 "dout_cmu_shared0_div4",
562 "dout_cmu_shared2_div2",
563 "oscclk" };
564 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
565 "dout_cmu_shared2_div2" };
566 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
567 "dout_cmu_shared2_div2",
568 "oscclk" };
569 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared0_div4",
570 "dout_cmu_shared2_div2",
571 "oscclk" };
572 PNAME(mout_cmu_hsi0_usbdp_debug_p) = { "oscclk", "fout_shared2_pll" };
573 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
574 "dout_cmu_shared0_div4",
575 "dout_cmu_shared1_div4",
576 "dout_cmu_shared4_div3",
577 "dout_cmu_shared2_div2",
578 "fout_mmc_pll", "oscclk", "oscclk" };
579 PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
580 "fout_mmc_pll",
581 "dout_cmu_shared0_div4" };
582 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
583 PNAME(mout_cmu_hsi1_ufs_card_p) = { "oscclk", "dout_cmu_shared0_div4",
584 "dout_cmu_shared2_div2",
585 "oscclk" };
586 PNAME(mout_cmu_hsi1_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
587 "dout_cmu_shared2_div2",
588 "oscclk" };
589 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div3",
590 "dout_cmu_shared2_div2" };
591 PNAME(mout_cmu_hsi2_pcie_p) = { "oscclk", "fout_shared2_pll" };
592 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3",
593 "dout_cmu_shared4_div2",
594 "dout_cmu_shared0_div4",
595 "dout_cmu_shared1_div4",
596 "dout_cmu_shared4_div3",
597 "oscclk", "oscclk", "oscclk" };
598 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3",
599 "dout_cmu_shared4_div2",
600 "dout_cmu_shared0_div4",
601 "dout_cmu_shared1_div4",
602 "dout_cmu_shared4_div3",
603 "dout_cmu_shared2_div2",
604 "oscclk", "oscclk" };
605 PNAME(mout_cmu_mcsc_bus_p) = { "dout_cmu_shared0_div3",
606 "dout_cmu_shared4_div2",
607 "dout_cmu_shared0_div4",
608 "dout_cmu_shared1_div4",
609 "dout_cmu_shared4_div3",
610 "dout_cmu_shared2_div2",
611 "oscclk", "oscclk" };
612 PNAME(mout_cmu_mcsc_gdc_p) = { "dout_cmu_shared0_div3",
613 "dout_cmu_shared4_div2",
614 "dout_cmu_shared0_div4",
615 "dout_cmu_shared1_div4",
616 "dout_cmu_shared4_div3",
617 "dout_cmu_shared2_div2",
618 "oscclk", "oscclk" };
619 PNAME(mout_cmu_cmu_boost_cpu_p) = { "dout_cmu_shared0_div4",
620 "dout_cmu_shared1_div4",
621 "dout_cmu_shared2_div2",
622 "oscclk" };
623 PNAME(mout_cmu_mfc0_mfc0_p) = { "dout_cmu_shared4_div2",
624 "dout_cmu_shared0_div4",
625 "dout_cmu_shared4_div3",
626 "dout_cmu_shared2_div2" };
627 PNAME(mout_cmu_mfc0_wfd_p) = { "dout_cmu_shared4_div2",
628 "dout_cmu_shared0_div4",
629 "dout_cmu_shared4_div3",
630 "dout_cmu_shared2_div2" };
631 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
632 "dout_cmu_shared1_div4",
633 "dout_cmu_shared2_div2",
634 "oscclk" };
635 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll",
636 "fout_shared1_pll",
637 "dout_cmu_shared0_div2",
638 "dout_cmu_shared1_div2",
639 "fout_shared2_pll",
640 "dout_cmu_shared0_div4",
641 "dout_cmu_shared2_div2",
642 "oscclk" };
643 PNAME(mout_cmu_npu_bus_p) = { "dout_cmu_shared0_div2",
644 "dout_cmu_shared1_div2",
645 "fout_shared2_pll",
646 "dout_cmu_shared4_div2",
647 "fout_shared3_pll", "oscclk",
648 "oscclk", "oscclk" };
649 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
650 "dout_cmu_shared2_div2" };
651 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
652 "dout_cmu_shared2_div2" };
653 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
654 "dout_cmu_shared2_div2" };
655 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
656 "dout_cmu_shared2_div2" };
657 PNAME(mout_cmu_peris_bus_p) = { "dout_cmu_shared0_div4",
658 "dout_cmu_shared2_div2" };
659 PNAME(mout_cmu_ssp_bus_p) = { "dout_cmu_shared4_div2",
660 "dout_cmu_shared0_div4",
661 "dout_cmu_shared4_div3",
662 "dout_cmu_shared2_div2" };
663 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3",
664 "dout_cmu_shared4_div2",
665 "dout_cmu_shared0_div4",
666 "dout_cmu_shared1_div4",
667 "dout_cmu_shared4_div3",
668 "dout_cmu_shared2_div2",
669 "oscclk", "oscclk" };
670 PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
671 "dout_cmu_shared4_div2",
672 "dout_cmu_shared0_div4",
673 "dout_cmu_shared4_div3" };
674
675 /*
676 * Register name to clock name mangling strategy used in this file
677 *
678 * Replace PLL_CON{0,3}_PLL with CLK_MOUT_PLL and mout_pll
679 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
680 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
681 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
682 * Replace CLK_CON_DIV_PLL_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu
683 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
684 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
685 *
686 * For gates remove _UID _BLK _IPCLKPORT, _I and _RSTNSYNC
687 */
688
689 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
690 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
691 PLL_CON3_PLL_SHARED0, 4, 1),
692 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
693 PLL_CON3_PLL_SHARED1, 4, 1),
694 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
695 PLL_CON3_PLL_SHARED2, 4, 1),
696 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
697 PLL_CON3_PLL_SHARED3, 4, 1),
698 MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
699 PLL_CON0_PLL_SHARED4, 4, 1),
700 MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
701 PLL_CON0_PLL_MMC, 4, 1),
702 MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
703 PLL_CON0_PLL_G3D, 4, 1),
704 MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
705 mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
706 MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
707 mout_cmu_aud_cpu_p, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 2),
708 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus",
709 mout_cmu_bus0_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 2),
710 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus",
711 mout_cmu_bus1_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 2),
712 MUX(CLK_MOUT_CMU_BUS1_SSS, "mout_cmu_bus1_sss",
713 mout_cmu_bus1_sss_p, CLK_CON_MUX_MUX_CLKCMU_BUS1_SSS, 0, 2),
714 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0",
715 mout_cmu_cis_clk0_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1),
716 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1",
717 mout_cmu_cis_clk1_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1),
718 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2",
719 mout_cmu_cis_clk2_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1),
720 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3",
721 mout_cmu_cis_clk3_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1),
722 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4",
723 mout_cmu_cis_clk4_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 1),
724 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5",
725 mout_cmu_cis_clk5_p, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 1),
726 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost",
727 mout_cmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
728 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus",
729 mout_cmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
730 MUX(CLK_MOUT_CMU_CPUCL0_DBG_BUS, "mout_cmu_cpucl0_dbg_bus",
731 mout_cmu_cpucl0_dbg_bus_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG_BUS,
732 0, 2),
733 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
734 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
735 0, 2),
736 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
737 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
738 0, 2),
739 MUX(CLK_MOUT_CMU_CPUCL2_BUSP, "mout_cmu_cpucl2_busp",
740 mout_cmu_cpucl2_busp_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_BUSP,
741 0, 1),
742 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
743 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
744 0, 2),
745 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus",
746 mout_cmu_csis_bus_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 2),
747 MUX(CLK_MOUT_CMU_CSIS_OIS_MCU, "mout_cmu_csis_ois_mcu",
748 mout_cmu_csis_ois_mcu_p, CLK_CON_MUX_MUX_CLKCMU_CSIS_OIS_MCU,
749 0, 1),
750 MUX(CLK_MOUT_CMU_DNC_BUS, "mout_cmu_dnc_bus",
751 mout_cmu_dnc_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUS, 0, 2),
752 MUX(CLK_MOUT_CMU_DNC_BUSM, "mout_cmu_dnc_busm",
753 mout_cmu_dnc_busm_p, CLK_CON_MUX_MUX_CLKCMU_DNC_BUSM, 0, 2),
754 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus",
755 mout_cmu_dns_bus_p, CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
756 MUX(CLK_MOUT_CMU_DPU, "mout_cmu_dpu",
757 mout_cmu_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 1),
758 MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt",
759 mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2),
760 MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus",
761 mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2),
762 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d",
763 mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2),
764 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl",
765 mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1),
766 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm",
767 mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
768 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus",
769 mout_cmu_hsi0_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 1),
770 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
771 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
772 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
773 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
774 0, 2),
775 MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug",
776 mout_cmu_hsi0_usbdp_debug_p,
777 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2),
778 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus",
779 mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
780 MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card",
781 mout_cmu_hsi1_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_MMC_CARD,
782 0, 2),
783 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie",
784 mout_cmu_hsi1_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
785 MUX(CLK_MOUT_CMU_HSI1_UFS_CARD, "mout_cmu_hsi1_ufs_card",
786 mout_cmu_hsi1_ufs_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_CARD,
787 0, 2),
788 MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd",
789 mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD,
790 0, 1),
791 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus",
792 mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1),
793 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie",
794 mout_cmu_hsi2_pcie_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
795 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus",
796 mout_cmu_ipp_bus_p, CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
797 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus",
798 mout_cmu_itp_bus_p, CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
799 MUX(CLK_MOUT_CMU_MCSC_BUS, "mout_cmu_mcsc_bus",
800 mout_cmu_mcsc_bus_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_BUS, 0, 3),
801 MUX(CLK_MOUT_CMU_MCSC_GDC, "mout_cmu_mcsc_gdc",
802 mout_cmu_mcsc_gdc_p, CLK_CON_MUX_MUX_CLKCMU_MCSC_GDC, 0, 3),
803 MUX(CLK_MOUT_CMU_CMU_BOOST_CPU, "mout_cmu_cmu_boost_cpu",
804 mout_cmu_cmu_boost_cpu_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_CPU,
805 0, 2),
806 MUX(CLK_MOUT_CMU_MFC0_MFC0, "mout_cmu_mfc0_mfc0",
807 mout_cmu_mfc0_mfc0_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_MFC0, 0, 2),
808 MUX(CLK_MOUT_CMU_MFC0_WFD, "mout_cmu_mfc0_wfd",
809 mout_cmu_mfc0_wfd_p, CLK_CON_MUX_MUX_CLKCMU_MFC0_WFD, 0, 2),
810 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp",
811 mout_cmu_mif_busp_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
812 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
813 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
814 MUX(CLK_MOUT_CMU_NPU_BUS, "mout_cmu_npu_bus",
815 mout_cmu_npu_bus_p, CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
816 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
817 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
818 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip",
819 mout_cmu_peric0_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
820 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
821 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
822 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip",
823 mout_cmu_peric1_ip_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
824 MUX(CLK_MOUT_CMU_PERIS_BUS, "mout_cmu_peris_bus",
825 mout_cmu_peris_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
826 MUX(CLK_MOUT_CMU_SSP_BUS, "mout_cmu_ssp_bus",
827 mout_cmu_ssp_bus_p, CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, 0, 2),
828 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus",
829 mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
830 MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
831 mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
832 };
833
834 static const struct samsung_div_clock top_div_clks[] __initconst = {
835 /* SHARED0 region*/
836 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
837 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
838 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
839 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
840 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
841 CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
842
843 /* SHARED1 region*/
844 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
845 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
846 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
847 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
848 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
849 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
850
851 /* SHARED2 region */
852 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
853 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
854
855 /* SHARED4 region*/
856 DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
857 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
858 DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
859 CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
860 DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
861 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
862
863 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
864 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
865 DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
866 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
867 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
868 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
869 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
870 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
871 DIV(CLK_DOUT_CMU_BUS1_SSS, "dout_cmu_bus1_sss", "gout_cmu_bus1_sss",
872 CLK_CON_DIV_CLKCMU_BUS1_SSS, 0, 4),
873 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
874 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
875 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
876 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
877 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
878 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
879 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
880 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
881 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
882 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
883 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
884 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
885 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "mout_cmu_cmu_boost",
886 CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2),
887 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
888 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
889 DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug",
890 "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS,
891 0, 3),
892 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
893 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
894 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
895 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
896 DIV(CLK_DOUT_CMU_CPUCL2_BUSP, "dout_cmu_cpucl2_busp",
897 "gout_cmu_cpucl2_busp", CLK_CON_DIV_CLKCMU_CPUCL2_BUSP, 0, 4),
898 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
899 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
900 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
901 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
902 DIV(CLK_DOUT_CMU_CSIS_OIS_MCU, "dout_cmu_csis_ois_mcu",
903 "gout_cmu_csis_ois_mcu", CLK_CON_DIV_CLKCMU_CSIS_OIS_MCU, 0, 4),
904 DIV(CLK_DOUT_CMU_DNC_BUS, "dout_cmu_dnc_bus", "gout_cmu_dnc_bus",
905 CLK_CON_DIV_CLKCMU_DNC_BUS, 0, 4),
906 DIV(CLK_DOUT_CMU_DNC_BUSM, "dout_cmu_dnc_busm", "gout_cmu_dnc_busm",
907 CLK_CON_DIV_CLKCMU_DNC_BUSM, 0, 4),
908 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
909 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
910 DIV(CLK_DOUT_CMU_DSP_BUS, "dout_cmu_dsp_bus", "gout_cmu_dsp_bus",
911 CLK_CON_DIV_CLKCMU_DSP_BUS, 0, 4),
912 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
913 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
914 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
915 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
916 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
917 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
918 DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
919 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
920 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
921 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
922 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc", "gout_cmu_hsi0_dpgtc",
923 CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3),
924 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
925 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4),
926 DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug",
927 "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG,
928 0, 4),
929 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
930 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3),
931 DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card",
932 "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD,
933 0, 9),
934 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
935 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7),
936 DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card",
937 "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD,
938 0, 3),
939 DIV(CLK_DOUT_CMU_HSI1_UFS_EMBD, "dout_cmu_hsi1_ufs_embd",
940 "gout_cmu_hsi1_ufs_embd", CLK_CON_DIV_CLKCMU_HSI1_UFS_EMBD,
941 0, 3),
942 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
943 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
944 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
945 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7),
946 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
947 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
948 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
949 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
950 DIV(CLK_DOUT_CMU_MCSC_BUS, "dout_cmu_mcsc_bus", "gout_cmu_mcsc_bus",
951 CLK_CON_DIV_CLKCMU_MCSC_BUS, 0, 4),
952 DIV(CLK_DOUT_CMU_MCSC_GDC, "dout_cmu_mcsc_gdc", "gout_cmu_mcsc_gdc",
953 CLK_CON_DIV_CLKCMU_MCSC_GDC, 0, 4),
954 DIV(CLK_DOUT_CMU_CMU_BOOST_CPU, "dout_cmu_cmu_boost_cpu",
955 "mout_cmu_cmu_boost_cpu", CLK_CON_DIV_CLKCMU_CMU_BOOST_CPU,
956 0, 2),
957 DIV(CLK_DOUT_CMU_MFC0_MFC0, "dout_cmu_mfc0_mfc0", "gout_cmu_mfc0_mfc0",
958 CLK_CON_DIV_CLKCMU_MFC0_MFC0, 0, 4),
959 DIV(CLK_DOUT_CMU_MFC0_WFD, "dout_cmu_mfc0_wfd", "gout_cmu_mfc0_wfd",
960 CLK_CON_DIV_CLKCMU_MFC0_WFD, 0, 4),
961 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
962 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
963 DIV(CLK_DOUT_CMU_NPU_BUS, "dout_cmu_npu_bus", "gout_cmu_npu_bus",
964 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
965 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus", "gout_cmu_peric0_bus",
966 CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
967 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
968 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
969 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus", "gout_cmu_peric1_bus",
970 CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
971 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
972 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
973 DIV(CLK_DOUT_CMU_PERIS_BUS, "dout_cmu_peris_bus", "gout_cmu_peris_bus",
974 CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
975 DIV(CLK_DOUT_CMU_SSP_BUS, "dout_cmu_ssp_bus", "gout_cmu_ssp_bus",
976 CLK_CON_DIV_CLKCMU_SSP_BUS, 0, 4),
977 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
978 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
979 DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus",
980 CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
981 DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu",
982 CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4),
983 };
984
985 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
986 GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus",
987 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
988 GATE(CLK_GOUT_CMU_AUD_CPU, "gout_cmu_aud_cpu", "mout_cmu_aud_cpu",
989 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
990 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
991 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, CLK_IGNORE_UNUSED, 0),
992 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
993 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, CLK_IGNORE_UNUSED, 0),
994 GATE(CLK_GOUT_CMU_BUS1_SSS, "gout_cmu_bus1_sss", "mout_cmu_bus1_sss",
995 CLK_CON_GAT_GATE_CLKCMU_BUS1_SSS, 21, CLK_IGNORE_UNUSED, 0),
996 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
997 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
998 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
999 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1000 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1001 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1002 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1003 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1004 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1005 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1006 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1007 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1008 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1009 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IGNORE_UNUSED, 0),
1010 GATE(CLK_GOUT_CMU_CPUCL0_DBG_BUS, "gout_cmu_cpucl0_dbg_bus",
1011 "mout_cmu_cpucl0_dbg_bus", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1012 21, 0, 0),
1013 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1014 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1015 21, CLK_IGNORE_UNUSED, 0),
1016 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1017 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1018 21, CLK_IGNORE_UNUSED, 0),
1019 GATE(CLK_GOUT_CMU_CPUCL2_BUSP, "gout_cmu_cpucl2_busp",
1020 "mout_cmu_cpucl2_busp", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_BUSP,
1021 21, CLK_IGNORE_UNUSED, 0),
1022 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1023 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1024 21, CLK_IGNORE_UNUSED, 0),
1025 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1026 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1027 GATE(CLK_GOUT_CMU_CSIS_OIS_MCU, "gout_cmu_csis_ois_mcu",
1028 "mout_cmu_csis_ois_mcu", CLK_CON_GAT_GATE_CLKCMU_CSIS_OIS_MCU,
1029 21, 0, 0),
1030 GATE(CLK_GOUT_CMU_DNC_BUS, "gout_cmu_dnc_bus", "mout_cmu_dnc_bus",
1031 CLK_CON_GAT_GATE_CLKCMU_DNC_BUS, 21, 0, 0),
1032 GATE(CLK_GOUT_CMU_DNC_BUSM, "gout_cmu_dnc_busm", "mout_cmu_dnc_busm",
1033 CLK_CON_GAT_GATE_CLKCMU_DNC_BUSM, 21, 0, 0),
1034 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1035 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1036 GATE(CLK_GOUT_CMU_DPU, "gout_cmu_dpu", "mout_cmu_dpu",
1037 CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
1038 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_alt",
1039 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, CLK_IGNORE_UNUSED, 0),
1040 GATE(CLK_GOUT_CMU_DSP_BUS, "gout_cmu_dsp_bus", "mout_cmu_dsp_bus",
1041 CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 21, 0, 0),
1042 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1043 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1044 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1045 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1046 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1047 "fout_shared2_pll", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1048 21, 0, 0),
1049 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1050 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1051 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus",
1052 "mout_cmu_hsi0_bus", CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1053 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1054 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1055 21, 0, 0),
1056 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1057 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1058 21, 0, 0),
1059 GATE(CLK_GOUT_CMU_HSI0_USBDP_DEBUG, "gout_cmu_hsi0_usbdp_debug",
1060 "mout_cmu_hsi0_usbdp_debug", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDP_DEBUG,
1061 21, 0, 0),
1062 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1063 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1064 GATE(CLK_GOUT_CMU_HSI1_MMC_CARD, "gout_cmu_hsi1_mmc_card",
1065 "mout_cmu_hsi1_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_MMC_CARD,
1066 21, 0, 0),
1067 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie",
1068 "mout_cmu_hsi1_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
1069 21, 0, 0),
1070 GATE(CLK_GOUT_CMU_HSI1_UFS_CARD, "gout_cmu_hsi1_ufs_card",
1071 "mout_cmu_hsi1_ufs_card", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_CARD,
1072 21, 0, 0),
1073 GATE(CLK_GOUT_CMU_HSI1_UFS_EMBD, "gout_cmu_hsi1_ufs_embd",
1074 "mout_cmu_hsi1_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI1_UFS_EMBD,
1075 21, 0, 0),
1076 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1077 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1078 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie",
1079 "mout_cmu_hsi2_pcie", CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
1080 21, 0, 0),
1081 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1082 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1083 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1084 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1085 GATE(CLK_GOUT_CMU_MCSC_BUS, "gout_cmu_mcsc_bus", "mout_cmu_mcsc_bus",
1086 CLK_CON_GAT_GATE_CLKCMU_MCSC_BUS, 21, 0, 0),
1087 GATE(CLK_GOUT_CMU_MCSC_GDC, "gout_cmu_mcsc_gdc", "mout_cmu_mcsc_gdc",
1088 CLK_CON_GAT_GATE_CLKCMU_MCSC_GDC, 21, 0, 0),
1089 GATE(CLK_GOUT_CMU_MFC0_MFC0, "gout_cmu_mfc0_mfc0",
1090 "mout_cmu_mfc0_mfc0", CLK_CON_GAT_GATE_CLKCMU_MFC0_MFC0,
1091 21, 0, 0),
1092 GATE(CLK_GOUT_CMU_MFC0_WFD, "gout_cmu_mfc0_wfd", "mout_cmu_mfc0_wfd",
1093 CLK_CON_GAT_GATE_CLKCMU_MFC0_WFD, 21, 0, 0),
1094 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1095 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1096 GATE(CLK_GOUT_CMU_NPU_BUS, "gout_cmu_npu_bus", "mout_cmu_npu_bus",
1097 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
1098 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1099 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1100 21, 0, 0),
1101 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip",
1102 "mout_cmu_peric0_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
1103 21, 0, 0),
1104 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1105 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1106 21, 0, 0),
1107 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip",
1108 "mout_cmu_peric1_ip", CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
1109 21, 0, 0),
1110 GATE(CLK_GOUT_CMU_PERIS_BUS, "gout_cmu_peris_bus",
1111 "mout_cmu_peris_bus", CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS,
1112 21, CLK_IGNORE_UNUSED, 0),
1113 GATE(CLK_GOUT_CMU_SSP_BUS, "gout_cmu_ssp_bus", "mout_cmu_ssp_bus",
1114 CLK_CON_GAT_GATE_CLKCMU_SSP_BUS, 21, 0, 0),
1115 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1116 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1117 GATE(CLK_GOUT_CMU_VRA_BUS, "gout_cmu_vra_bus", "mout_cmu_vra_bus",
1118 CLK_CON_GAT_GATE_CLKCMU_VRA_BUS, 21, 0, 0),
1119 };
1120
1121 static const struct samsung_cmu_info top_cmu_info __initconst = {
1122 .pll_clks = top_pll_clks,
1123 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1124 .mux_clks = top_mux_clks,
1125 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1126 .div_clks = top_div_clks,
1127 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1128 .gate_clks = top_gate_clks,
1129 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1130 .nr_clk_ids = CLKS_NR_TOP,
1131 .clk_regs = top_clk_regs,
1132 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1133 };
1134
exynos990_cmu_top_init(struct device_node * np)1135 static void __init exynos990_cmu_top_init(struct device_node *np)
1136 {
1137 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1138 }
1139
1140 /* Register CMU_TOP early, as it's a dependency for other early domains */
1141 CLK_OF_DECLARE(exynos990_cmu_top, "samsung,exynos990-cmu-top",
1142 exynos990_cmu_top_init);
1143
1144 /* ---- CMU_HSI0 ------------------------------------------------------------ */
1145
1146 /* Register Offset definitions for CMU_HSI0 (0x10a00000) */
1147 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0600
1148 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0620
1149 #define PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER 0x0630
1150 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0610
1151 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x2004
1152 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK 0x2018
1153 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2014
1154 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2020
1155 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK 0x2044
1156 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2008
1157 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x200c
1158 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x2010
1159 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK 0x201c
1160 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2024
1161 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2028
1162 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x202c
1163 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2034
1164 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x203c
1165 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2040
1166 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2030
1167 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
1168 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK 0x2048
1169 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x2038
1170
1171 static const unsigned long hsi0_clk_regs[] __initconst = {
1172 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1173 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1174 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1175 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1176 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1177 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1178 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1179 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
1180 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1181 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1182 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1183 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1184 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1185 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1186 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1187 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1188 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1189 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1190 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1191 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1192 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1193 };
1194
1195 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
1196 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk", "dout_cmu_hsi0_usb31drd" };
1197 PNAME(mout_hsi0_usbdp_debug_user_p) = { "oscclk",
1198 "dout_cmu_hsi0_usbdp_debug" };
1199 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
1200
1201 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
1202 MUX(CLK_MOUT_HSI0_BUS_USER, "mout_hsi0_bus_user",
1203 mout_hsi0_bus_user_p, PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
1204 4, 1),
1205 MUX(CLK_MOUT_HSI0_USB31DRD_USER, "mout_hsi0_usb31drd_user",
1206 mout_hsi0_usb31drd_user_p, PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
1207 4, 1),
1208 MUX(CLK_MOUT_HSI0_USBDP_DEBUG_USER, "mout_hsi0_usbdp_debug_user",
1209 mout_hsi0_usbdp_debug_user_p,
1210 PLL_CON0_MUX_CLKCMU_HSI0_USBDP_DEBUG_USER,
1211 4, 1),
1212 MUX(CLK_MOUT_HSI0_DPGTC_USER, "mout_hsi0_dpgtc_user",
1213 mout_hsi0_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
1214 4, 1),
1215 };
1216
1217 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
1218 GATE(CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK,
1219 "gout_hsi0_dp_link_dp_gtc_clk", "mout_hsi0_dpgtc_user",
1220 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
1221 21, 0, 0),
1222 GATE(CLK_GOUT_HSI0_DP_LINK_PCLK,
1223 "gout_hsi0_dp_link_pclk", "mout_hsi0_bus_user",
1224 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
1225 21, 0, 0),
1226 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
1227 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus_user",
1228 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
1229 21, 0, 0),
1230 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK,
1231 "gout_hsi0_lhm_axi_p_hsi0_clk", "mout_hsi0_bus_user",
1232 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
1233 21, CLK_IS_CRITICAL, 0),
1234 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK,
1235 "gout_hsi0_ppmu_hsi0_bus1_aclk", "mout_hsi0_bus_user",
1236 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_ACLK,
1237 21, 0, 0),
1238 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK,
1239 "gout_hsi0_ppmu_hsi0_bus1_pclk", "mout_hsi0_bus_user",
1240 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS1_IPCLKPORT_PCLK,
1241 21, 0, 0),
1242 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
1243 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus_user",
1244 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
1245 21, 0, 0),
1246 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
1247 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus_user",
1248 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
1249 21, CLK_IGNORE_UNUSED, 0),
1250 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
1251 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus_user",
1252 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
1253 21, 0, 0),
1254 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
1255 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus_user",
1256 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
1257 21, 0, 0),
1258 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
1259 "gout_hsi0_usb31drd_bus_clk_early",
1260 "mout_hsi0_bus_user",
1261 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
1262 21, 0, 0),
1263 GATE(CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40,
1264 "gout_hsi0_usb31drd_usb31drd_ref_clk_40",
1265 "mout_hsi0_usb31drd_user",
1266 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
1267 21, 0, 0),
1268 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL,
1269 "gout_hsi0_usb31drd_usbdpphy_ref_soc_pll",
1270 "mout_hsi0_usbdp_debug_user",
1271 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
1272 21, 0, 0),
1273 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB,
1274 "gout_hsi0_usb31drd_ipclkport_i_usbdpphy_scl_apb_pclk",
1275 "mout_hsi0_bus_user",
1276 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
1277 21, 0, 0),
1278 GATE(CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK,
1279 "gout_hsi0_usb31drd_usbpcs_apb_clk",
1280 "mout_hsi0_bus_user",
1281 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
1282 21, 0, 0),
1283 GATE(CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK,
1284 "gout_hsi0_vgen_lite_ipclkport_clk", "mout_hsi0_bus_user",
1285 CLK_CON_GAT_GOUT_BLK_HSI0_UID_VGEN_LITE_HSI0_IPCLKPORT_CLK,
1286 21, 0, 0),
1287 GATE(CLK_GOUT_HSI0_CMU_HSI0_PCLK,
1288 "gout_hsi0_cmu_hsi0_pclk", "mout_hsi0_bus_user",
1289 CLK_CON_GAT_GOUT_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
1290 21, CLK_IGNORE_UNUSED, 0),
1291 GATE(CLK_GOUT_HSI0_XIU_D_HSI0_ACLK,
1292 "gout_hsi0_xiu_d_hsi0_aclk", "mout_hsi0_bus_user",
1293 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D_HSI0_IPCLKPORT_ACLK,
1294 21, CLK_IGNORE_UNUSED, 0),
1295 };
1296
1297 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
1298 .mux_clks = hsi0_mux_clks,
1299 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
1300 .gate_clks = hsi0_gate_clks,
1301 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
1302 .nr_clk_ids = CLKS_NR_HSI0,
1303 .clk_regs = hsi0_clk_regs,
1304 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
1305 .clk_name = "bus",
1306 };
1307
1308 /* ----- platform_driver ----- */
1309
exynos990_cmu_probe(struct platform_device * pdev)1310 static int __init exynos990_cmu_probe(struct platform_device *pdev)
1311 {
1312 const struct samsung_cmu_info *info;
1313 struct device *dev = &pdev->dev;
1314
1315 info = of_device_get_match_data(dev);
1316 exynos_arm64_register_cmu(dev, dev->of_node, info);
1317
1318 return 0;
1319 }
1320
1321 static const struct of_device_id exynos990_cmu_of_match[] = {
1322 {
1323 .compatible = "samsung,exynos990-cmu-hsi0",
1324 .data = &hsi0_cmu_info,
1325 },
1326 { },
1327 };
1328
1329 static struct platform_driver exynos990_cmu_driver __refdata = {
1330 .driver = {
1331 .name = "exynos990-cmu",
1332 .of_match_table = exynos990_cmu_of_match,
1333 .suppress_bind_attrs = true,
1334 },
1335 .probe = exynos990_cmu_probe,
1336 };
1337
exynos990_cmu_init(void)1338 static int __init exynos990_cmu_init(void)
1339 {
1340 return platform_driver_register(&exynos990_cmu_driver);
1341 }
1342
1343 core_initcall(exynos990_cmu_init);
1344