1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Samsung Exynos 990 SoC device tree source
4 *
5 * Copyright (c) 2024, Igor Belwon <[email protected]>
6 */
7
8#include <dt-bindings/clock/samsung,exynos990.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12	compatible = "samsung,exynos990";
13	#address-cells = <2>;
14	#size-cells = <1>;
15
16	interrupt-parent = <&gic>;
17
18	aliases {
19		pinctrl0 = &pinctrl_alive;
20		pinctrl1 = &pinctrl_cmgp;
21		pinctrl2 = &pinctrl_hsi1;
22		pinctrl3 = &pinctrl_hsi2;
23		pinctrl4 = &pinctrl_peric0;
24		pinctrl5 = &pinctrl_peric1;
25		pinctrl6 = &pinctrl_vts;
26	};
27
28	arm-a55-pmu {
29		compatible = "arm,cortex-a55-pmu";
30		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
31			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
32			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
33			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
34
35		interrupt-affinity = <&cpu0>,
36				     <&cpu1>,
37				     <&cpu2>,
38				     <&cpu3>;
39	};
40
41	arm-a76-pmu {
42		compatible = "arm,cortex-a76-pmu";
43		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
44			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
45
46		interrupt-affinity = <&cpu4>,
47				     <&cpu5>;
48	};
49
50	mongoose-m5-pmu {
51		compatible = "samsung,mongoose-pmu";
52		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
53			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
54
55		interrupt-affinity = <&cpu6>,
56				     <&cpu7>;
57	};
58
59	cpus {
60		#address-cells = <1>;
61		#size-cells = <0>;
62
63		cpu-map {
64			cluster0 {
65				core0 {
66					cpu = <&cpu0>;
67				};
68
69				core1 {
70					cpu = <&cpu1>;
71				};
72
73				core2 {
74					cpu = <&cpu2>;
75				};
76
77				core3 {
78					cpu = <&cpu3>;
79				};
80			};
81
82			cluster1 {
83				core0 {
84					cpu = <&cpu4>;
85				};
86
87				core1 {
88					cpu = <&cpu5>;
89				};
90			};
91
92			cluster2 {
93				core0 {
94					cpu = <&cpu6>;
95				};
96
97				core1 {
98					cpu = <&cpu7>;
99				};
100			};
101		};
102
103		cpu0: cpu@0 {
104			device_type = "cpu";
105			compatible = "arm,cortex-a55";
106			reg = <0x0>;
107			enable-method = "psci";
108		};
109
110		cpu1: cpu@1 {
111			device_type = "cpu";
112			compatible = "arm,cortex-a55";
113			reg = <0x1>;
114			enable-method = "psci";
115		};
116
117		cpu2: cpu@2 {
118			device_type = "cpu";
119			compatible = "arm,cortex-a55";
120			reg = <0x2>;
121			enable-method = "psci";
122		};
123
124		cpu3: cpu@3 {
125			device_type = "cpu";
126			compatible = "arm,cortex-a55";
127			reg = <0x3>;
128			enable-method = "psci";
129		};
130
131		cpu4: cpu@100 {
132			device_type = "cpu";
133			compatible = "arm,cortex-a76";
134			reg = <0x4>;
135			enable-method = "psci";
136		};
137
138		cpu5: cpu@101 {
139			device_type = "cpu";
140			compatible = "arm,cortex-a76";
141			reg = <0x5>;
142			enable-method = "psci";
143		};
144
145		cpu6: cpu@200 {
146			device_type = "cpu";
147			compatible = "samsung,mongoose-m5";
148			reg = <0x6>;
149			enable-method = "psci";
150		};
151
152		cpu7: cpu@201 {
153			device_type = "cpu";
154			compatible = "samsung,mongoose-m5";
155			reg = <0x7>;
156			enable-method = "psci";
157		};
158	};
159
160	oscclk: clock-osc {
161		compatible = "fixed-clock";
162		#clock-cells = <0>;
163		clock-output-names = "oscclk";
164	};
165
166	psci {
167		compatible = "arm,psci-0.2";
168		method = "hvc";
169	};
170
171	soc: soc@0 {
172		compatible = "simple-bus";
173		ranges = <0x0 0x0 0x0 0x20000000>;
174
175		#address-cells = <1>;
176		#size-cells = <1>;
177
178		chipid@10000000 {
179			compatible = "samsung,exynos990-chipid",
180				     "samsung,exynos850-chipid";
181			reg = <0x10000000 0x100>;
182		};
183
184		gic: interrupt-controller@10101000 {
185			compatible = "arm,gic-400";
186			reg = <0x10101000 0x1000>,
187			      <0x10102000 0x1000>,
188			      <0x10104000 0x2000>,
189			      <0x10106000 0x2000>;
190			#interrupt-cells = <3>;
191			interrupt-controller;
192			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
193						 IRQ_TYPE_LEVEL_HIGH)>;
194			#address-cells = <0>;
195			#size-cells = <1>;
196		};
197
198		pinctrl_peric0: pinctrl@10430000 {
199			compatible = "samsung,exynos990-pinctrl";
200			reg = <0x10430000 0x1000>;
201			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
202		};
203
204		pinctrl_peric1: pinctrl@10730000 {
205			compatible = "samsung,exynos990-pinctrl";
206			reg = <0x10730000 0x1000>;
207			interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
208		};
209
210		cmu_hsi0: clock-controller@10a00000 {
211			compatible = "samsung,exynos990-cmu-hsi0";
212			reg = <0x10a00000 0x8000>;
213			#clock-cells = <1>;
214
215			clocks = <&oscclk>,
216				 <&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
217				 <&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
218				 <&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
219				 <&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
220			clock-names = "oscclk",
221				      "bus",
222				      "usb31drd",
223				      "usbdp_debug",
224				      "dpgtc";
225		};
226
227		pinctrl_hsi1: pinctrl@13040000 {
228			compatible = "samsung,exynos990-pinctrl";
229			reg = <0x13040000 0x1000>;
230			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
231		};
232
233		pinctrl_hsi2: pinctrl@13c30000 {
234			compatible = "samsung,exynos990-pinctrl";
235			reg = <0x13c30000 0x1000>;
236			interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
237		};
238
239		pinctrl_vts: pinctrl@15580000 {
240			compatible = "samsung,exynos990-pinctrl";
241			reg = <0x15580000 0x1000>;
242		};
243
244		pinctrl_alive: pinctrl@15850000 {
245			compatible = "samsung,exynos990-pinctrl";
246			reg = <0x15850000 0x1000>;
247
248			wakeup-interrupt-controller {
249				compatible = "samsung,exynos990-wakeup-eint",
250					     "samsung,exynos850-wakeup-eint",
251					     "samsung,exynos7-wakeup-eint";
252			};
253		};
254
255		pmu_system_controller: system-controller@15860000 {
256			compatible = "samsung,exynos990-pmu",
257				     "samsung,exynos7-pmu", "syscon";
258			reg = <0x15860000 0x10000>;
259
260			reboot: syscon-reboot {
261				compatible = "syscon-reboot";
262				regmap = <&pmu_system_controller>;
263				offset = <0x3a00>; /* SWRESET */
264				mask = <0x2>; /* SWRESET_TRIGGER */
265				value = <0x2>;
266			};
267		};
268
269		pinctrl_cmgp: pinctrl@15c30000 {
270			compatible = "samsung,exynos990-pinctrl";
271			reg = <0x15c30000 0x1000>;
272		};
273
274		cmu_top: clock-controller@1a330000 {
275			compatible = "samsung,exynos990-cmu-top";
276			reg = <0x1a330000 0x8000>;
277			#clock-cells = <1>;
278
279			clocks = <&oscclk>;
280			clock-names = "oscclk";
281		};
282	};
283
284	timer {
285		compatible = "arm,armv8-timer";
286		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
287			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
288			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
289			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
290
291		/*
292		 * Non-updatable, broken stock Samsung bootloader does not
293		 * configure CNTFRQ_EL0
294		 */
295		clock-frequency = <26000000>;
296	};
297};
298
299#include "exynos990-pinctrl.dtsi"
300