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/linux-6.14.4/arch/x86/kernel/cpu/
Dintel.c264 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
270 if (c->x86_power & (1 << 8)) { in early_init_intel()
356 boot_cpu_data.x86_stepping < 8) { in ppro_with_ram_bug()
416 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
448 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
462 case 6: /* PII/PIII only like movsl with 8-byte alignment */ in intel_workarounds()
465 case 15: /* P4 is OK down to 8-byte alignment */ in intel_workarounds()
535 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) in init_intel()
593 case 8: in init_intel()
671 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
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/linux-6.14.4/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu_v13_0_6_pmfw.h49 /*8*/ FEATURE_DPM_XGMI = 8,
165 uint64_t GfxclkFrequencyAcc[8];
185 uint64_t XgmiReadBandwidthAcc[8];
186 uint64_t XgmiWriteBandwidthAcc[8];
208 uint32_t GfxclkFrequency[8];
212 uint64_t PublicSerialNumber_XCD[8];
216 uint64_t XgmiReadDataSizeAcc[8];//in KByte
217 uint64_t XgmiWriteDataSizeAcc[8];//in KByte
236 uint32_t GfxBusy[8];
237 uint64_t GfxBusyAcc[8];
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/linux-6.14.4/Documentation/devicetree/bindings/mips/img/
Dxilfpga.txt21 - 8Kbyte RAM at 0x1000_0000
28 - 8Kbyte BootRAM at 0x1FC0_0000
/linux-6.14.4/Documentation/admin-guide/auxdisplay/
Dcfag12864b.rst38 :Pages: 8 each controller
41 :Memory size: 2 * 8 * 64 * 1 = 1024 bytes = 1 Kbyte
60 Data 4 ( 6)------------------------------( 8) Data 4
62 Data 6 ( 8)------------------------------(10) Data 6
87 It has a size of 1024 bytes = 1 Kbyte.
/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dmicrochip,mchp48l640.yaml13 The Microchip 48l640 is a 8KByte EERAM connected via SPI.
/linux-6.14.4/arch/microblaze/kernel/
Dvmlinux.lds.S47 . = ALIGN (8) ;
51 . = _fdt_start + 0x10000; /* Pad up to 64kbyte */
66 . = ALIGN(8);
77 . = ALIGN(8);
/linux-6.14.4/Documentation/virt/kvm/devices/
Darm-vgic.rst29 This address needs to be 4K aligned and the region covers 4 KByte.
34 This address needs to be 4K aligned and the region covers 8 KByte.
/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0_3_cleaner_shader.asm52 s_mov_b32 m0, 0x00000058 // Loop 96/8=12 times (loop unrolled for performance)
63 s_sub_u32 m0, m0, 8
77 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte)
81 // Each FirstWave of WorkGroup clears 64kbyte block
Dgfx_v10_3_0_cleaner_shader.asm54 s_mov_b32 s2, 0x00000038 // Loop 64/8=8 times (loop unrolled for performance)
69 s_sub_u32 s2, s2, 8
81 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte)
85 // Each FirstWave of WorkGroup clears 64kbyte block
Dgfx_v9_4_2_cleaner_shader.asm60 s_mov_b32 s2, 0x00000078 // Loop 128/8=16 times (loop unrolled for performance)
74 s_sub_u32 s2, s2, 8
91 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byt…
95 // Each FirstWave of WorkGroup clears 64kbyte block
Dgfx_v9_4_3_cleaner_shader.asm60 s_mov_b32 s2, 0x00000078 // Loop 128/8=16 times (loop unrolled for performance)
74 s_sub_u32 s2, s2, 8
91 …v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byt…
95 // Each FirstWave of WorkGroup clears 64kbyte block
/linux-6.14.4/drivers/media/platform/via/
Dvia-camera.h21 #define VCR_TSC_COUNT 0x07fff0 /* KByte or packet count */
32 #define VCR_CI_CCIR601_8 0 /* CCIR601 input stream, 8 bit */
33 #define VCR_CI_CCIR656_8 0x00000010 /* ... CCIR656, 8 bit */
87 #define VCR_VS_STRIDE 0x00001ff0 /* Stride (8-byte units) */
/linux-6.14.4/Documentation/networking/
Deql.rst194 (Hereafter known as the 8-hour PPP Hate Festival). Perhaps later this
235 From [email protected] Wed Feb 8 19:08:09 1995
264 a 486DX2/66 with a Cyclom-8Ys and a 486SLC/40 with a Cyclom-16Y.
372 transfer of up to 7.5 Kbyte/s on one go, but averaged around
373 6.4 Kbyte/s, which I think is pretty cool. :)
D6pack.rst76 TNCs contain a 64kByte EPROM, the lower half of which is used for
94 function has been changed in the 2.1.8x kernels.
/linux-6.14.4/include/video/
Dsticore.h11 #define STI_REGION_MAX 8 /* hardcoded STI constants */
61 u32 offset : 14; /* offset in 4kbyte page */
66 u32 length : 14; /* length in 4kbyte page */
/linux-6.14.4/Documentation/virt/hyperv/
Dvmbus.rst80 space in three parts: 1) the 4 Kbyte header page, 2) the memory
92 passed to Hyper-V as a 4 Kbyte area. But the memory for the actual
177 an 8-bit x86/x64 interrupt vector, or an arm64 PPI INTID). Because
/linux-6.14.4/kernel/bpf/
Dmemalloc.c33 * Every allocated objected is padded with extra 8 bytes that contains
40 /* similar to kmalloc, but sizeof == 8 bucket is gone */
42 3, /* 8 */
74 return size_index[(size - 1) / 8] - 1; in bpf_mem_cache_idx()
144 void __percpu *pptr = __alloc_percpu_gfp(c->unit_size, 8, flags); in __alloc()
457 * 64*16 + 64*32 + 64*64 + 64*96 + 64*128 + 64*196 + 64*256 + 32*512 + 16*1024 + 8*2048 + 4*4096
458 * == ~ 116 Kbyte using below heuristic.
460 * consume ~ 11 Kbyte per cpu.
480 * 8k allocs and above low == 1, high == 3, batch == 1. in init_refill_work()
525 pc = __alloc_percpu_gfp(sizeof(*pc), 8, GFP_KERNEL); in bpf_mem_alloc_init()
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/linux-6.14.4/include/uapi/linux/
Dpci_regs.h71 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
76 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
77 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
78 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
85 #define PCI_BIST 0x0f /* 8 bits */
125 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
126 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
127 #define PCI_MIN_GNT 0x3e /* 8 bits */
128 #define PCI_MAX_LAT 0x3f /* 8 bits */
265 #define PCI_PM_SIZEOF 8
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/linux-6.14.4/drivers/misc/eeprom/
Dat25.c33 #define FM25_SN_LEN 8 /* serial number length */
105 if (msg_offset >= BIT(at25->addrlen * 8)) in at25_ee_read()
112 /* 8/16/24-bit address is written MSB first */ in at25_ee_read()
118 *cp++ = msg_offset >> 8; in at25_ee_read()
244 if (offset >= BIT(at25->addrlen * 8)) in at25_ee_write()
248 /* 8/16/24-bit address is written MSB first */ in at25_ee_write()
254 *cp++ = offset >> 8; in at25_ee_write()
359 case 8: in at25_fw_to_chip()
407 if (id[8]) { in at25_fram_to_chip()
474 /* For now we only support 8/16/24 bit addressing */ in at25_probe()
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/linux-6.14.4/Documentation/filesystems/
Dsquashfs.rst52 compressed inode is on average 8 bytes in length (the exact length varies on
173 Metadata (inodes and directories) are compressed in 8Kbyte blocks. Each
238 Larger files use multiple slots, with 1.75 TiB files using all 8 slots.
290 The xattr lists are packed into compressed 8K metadata blocks.
/linux-6.14.4/drivers/scsi/
Dsr_ioctl.c51 cgc.cmd[8] = 12; /* LSB of length */ in sr_read_tochdr()
86 cgc.cmd[8] = 12; /* LSB of length */ in sr_read_tocentry()
103 tocentry->cdte_addr.lba = (((((buffer[8] << 8) + buffer[9]) << 8) in sr_read_tocentry()
104 + buffer[10]) << 8) + buffer[11]; in sr_read_tocentry()
154 cgc.cmd[8] = trk1_te.cdte_addr.msf.frame; in sr_fake_playtrkind()
174 cgc.cmd[8] = ti->cdti_ind1; in sr_play_trkind()
406 cgc.cmd[8] = 24; in sr_get_mcn()
439 speed *= 177; /* Nx to kbyte/s */ in sr_select_speed()
443 cgc.cmd[2] = (speed >> 8) & 0xff; /* MSB for speed (in kbytes/sec) */ in sr_select_speed()
501 cgc.cmd[4] = (unsigned char) (lba >> 8) & 0xff; in sr_read_cd()
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/linux-6.14.4/include/linux/
Dhyperv.h169 * If the requested ring buffer size is at least 8 times the size of the
174 * The factor of 8 is somewhat arbitrary. The goal is to prevent adding a
178 * on ARM64 with 64 Kbyte page size, we don't want to take 64 Kbytes for the
179 * header from a 128 Kbyte allocation, leaving only 64 Kbytes for the ring.
184 ((payload_sz) >= 8 * sizeof(struct hv_ring_buffer) ? \
254 * 2 . 4 (Windows 8, WS2012)
418 u32 reserved; /* for alignment to a 8-byte boundary */
453 ((struct vmpacket_descriptor)__packet)->offset8 * 8)
457 ((struct vmpacket_descriptor)__packet)->offset8) * 8)
492 CHANNELMSG_GPADL_HEADER = 8,
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/linux-6.14.4/drivers/net/wireless/intel/iwlwifi/
Diwl-fh.h30 * Driver must allocate a 4KByte buffer that is for keeping the
59 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
76 return TFH_TFDQ_CBB_TABLE + 8 * chnl; in FH_MEM_CBBC_QUEUE()
96 * Bits 9:8:
106 #define TFH_CHUNK_SIZE_128 BIT(8)
163 * (typically 4K, although 8K or 16K are also selectable by driver).
168 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
170 * Driver sets physical address [35:8] of base of RBD circular buffer
173 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
192 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
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/linux-6.14.4/arch/arm/mm/
DKconfig36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
774 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
/linux-6.14.4/sound/pci/rme9652/
Drme9652.c137 #define RME9652_DS (1<<8) /* Doule Speed 0=44.1/48, 1=88.2/96 Khz */
251 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
256 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
275 /* channels 8 and 9 are S/PDIF */
339 rme9652->period_bytes = 1 << ((rme9652_decode_latency(i) + 8)); in rme9652_compute_period_size()
400 /* reset the FIFO pointer to zero. We do this by writing to 8 in rme9652_reset_hw_pointer()
406 for (i = 0; i < 8; i++) { in rme9652_reset_hw_pointer()
628 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) { in rme9652_spdif_write_byte()
647 for (i = 0, mask = 0x80; i < 8; i++, mask >>= 1) { in rme9652_spdif_read_byte()
1700 if (((i + 1) % 8) == 0) { in snd_rme9652_proc_read()
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