Lines Matching +full:8 +full:kbyte

30  * Driver must allocate a 4KByte buffer that is for keeping the
59  *  27-0: TFD CB physical base address [35:8], must be 256-byte aligned
76 		return TFH_TFDQ_CBB_TABLE + 8 * chnl;  in FH_MEM_CBBC_QUEUE()
96  * Bits 9:8:
106 #define TFH_CHUNK_SIZE_128			BIT(8)
163  *     (typically 4K, although 8K or 16K are also selectable by driver).
168  *     27-0:  Receive Buffer physical address bits [35:8], 256-byte aligned
170  *     Driver sets physical address [35:8] of base of RBD circular buffer
173  * 2)  Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
192  * RBs), should be 8 after preparing the first 8 RBs (for example), and must
195  * NOTE:  DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
220  * Physical base address of 8-byte Rx Status buffer.
229  *  27-0:  RBD CD physical base address [35:8], must be 256-byte aligned.
260  * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
263  * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
332 #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
344 #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8)
352 #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
355 #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8)
357 #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8)
446  * Device has one configuration register for each of 8 Tx DMA/FIFO channels
469 #define FH_TCSR_CHNL_NUM                            (8)
566 #define RX_QUEUE_SIZE_LOG                     8
678  * Tx frame, up to 8 KBytes in size.