Lines Matching +full:8 +full:kbyte
71 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
76 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
77 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
78 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
85 #define PCI_BIST 0x0f /* 8 bits */
125 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
126 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
127 #define PCI_MIN_GNT 0x3e /* 8 bits */
128 #define PCI_MAX_LAT 0x3f /* 8 bits */
265 #define PCI_PM_SIZEOF 8
279 #define PCI_AGP_COMMAND 8 /* Control register */
296 #define PCI_CAP_VPD_SIZEOF 8
331 #define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
374 #define PCI_EA_FIRST_ENT_BRIDGE 8 /* First EA Entry for Bridges */
381 #define PCI_EA_SUB_BUS_SHIFT 8
388 #define PCI_EA_BEI_ROM 8 /* Expansion ROM */
410 #define PCI_EA_MAX_OFFSET 8 /* MaxOffset (resource length) */
421 #define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
422 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
423 #define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
430 #define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
450 #define PCI_X_ECC_CSR 8 /* ECC control and status */
451 #define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */
687 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */
696 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
851 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
862 #define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */
864 #define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff)
911 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
916 #define PCI_EXT_CAP_ARI_SIZEOF 8
927 #define PCI_EXT_CAP_ATS_SIZEOF 8
951 #define PCI_EXT_CAP_PASID_SIZEOF 8
992 #define PCI_EXT_CAP_LTR_SIZEOF 8
1011 #define PCI_SATA_SIZEOF_SHORT 8
1017 #define PCI_REBAR_CTRL 8 /* control register */
1022 #define PCI_REBAR_CTRL_BAR_SHIFT 8 /* shift for BAR size */
1048 #define PCI_TPH_CTRL 8 /* control register */