| /linux-6.14.4/arch/arm64/crypto/ |
| D | sm4-ce-asm.h | 12 sm4e b0.4s, v24.4s; \
13 sm4e b0.4s, v25.4s; \
14 sm4e b0.4s, v26.4s; \
15 sm4e b0.4s, v27.4s; \
16 sm4e b0.4s, v28.4s; \
17 sm4e b0.4s, v29.4s; \
18 sm4e b0.4s, v30.4s; \
19 sm4e b0.4s, v31.4s; \
20 rev64 b0.4s, b0.4s; \
29 sm4e b0.4s, v24.4s; \
[all …]
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| D | chacha-neon-core.S | 42 ld1 {v12.4s}, [x10]
46 add v0.4s, v0.4s, v1.4s
51 add v2.4s, v2.4s, v3.4s
53 shl v1.4s, v4.4s, #12
54 sri v1.4s, v4.4s, #20
57 add v0.4s, v0.4s, v1.4s
62 add v2.4s, v2.4s, v3.4s
64 shl v1.4s, v4.4s, #7
65 sri v1.4s, v4.4s, #25
68 ext v1.16b, v1.16b, v1.16b, #4
[all …]
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| D | sm4-neon-core.S | 41 zip1 RTMP0.4s, s0.4s, s1.4s; \
42 zip1 RTMP1.4s, s2.4s, s3.4s; \
43 zip2 RTMP2.4s, s0.4s, s1.4s; \
44 zip2 RTMP3.4s, s2.4s, s3.4s; \
51 zip1 RTMP0.4s, s0.4s, s1.4s; \
52 zip1 RTMP1.4s, s2.4s, s3.4s; \
53 zip2 RTMP2.4s, s0.4s, s1.4s; \
54 zip2 RTMP3.4s, s2.4s, s3.4s; \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
56 zip1 RTMP5.4s, s6.4s, s7.4s; \
[all …]
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| D | sm4-ce-cipher-core.S | 6 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8
7 .set .Lv\b\().4s, \b
19 ld1 {v8.4s}, [x2]
20 ld1 {v0.4s-v3.4s}, [x0], #64
22 ld1 {v4.4s-v7.4s}, [x0]
23 sm4e v8.4s, v0.4s
24 sm4e v8.4s, v1.4s
25 sm4e v8.4s, v2.4s
26 sm4e v8.4s, v3.4s
27 sm4e v8.4s, v4.4s
[all …]
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| D | sha2-ce-core.S | 3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
45 sha256su0 v\s0\().4s, v\s1\().4s
47 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
54 .align 4
[all …]
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| D | sm3-ce-core.S | 3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
12 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
13 .set .Lv\b\().4s, \b
45 sm3ss1 v5.4s, v8.4s, \t0\().4s, v9.4s
46 shl \t1\().4s, \t0\().4s, #1
47 sri \t1\().4s, \t0\().4s, #31
48 sm3tt1\ab v8.4s, v5.4s, v10.4s, \i
49 sm3tt2\ab v9.4s, v5.4s, \s0\().4s, \i
57 sm3partw1 \s4\().4s, \s0\().4s, \s3\().4s
68 sm3partw2 \s4\().4s, v7.4s, v6.4s
[all …]
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| D | sha1-ce-core.S | 3 * sha1-ce-core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
36 add t1.4s, v\s0\().4s, \rc\().4s
39 sha1\op dg0q, \dg1, t0.4s
41 sha1\op dg0q, dg1s, t0.4s
45 add t0.4s, v\s0\().4s, \rc\().4s
48 sha1\op dg0q, dg2s, t1.4s
53 sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
55 sha1su1 v\s0\().4s, v\s3\().4s
70 loadrc k0.4s, 0x5a827999, w6
71 loadrc k1.4s, 0x6ed9eba1, w6
[all …]
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| D | nh-neon-core.S | 41 ld1 {\k3\().4s}, [KEY], #16
44 add T0.4s, T3.4s, \k0\().4s
45 add T1.4s, T3.4s, \k1\().4s
46 add T2.4s, T3.4s, \k2\().4s
47 add T3.4s, T3.4s, \k3\().4s
54 umlal PASS0_SUMS.2d, T0.2s, T4.2s
55 umlal PASS1_SUMS.2d, T1.2s, T5.2s
56 umlal PASS2_SUMS.2d, T2.2s, T6.2s
57 umlal PASS3_SUMS.2d, T3.2s, T7.2s
64 * It's guaranteed that message_len % 16 == 0.
[all …]
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| D | sm4-ce-gcm-core.S | 19 .set .Lv\b\().4s, \b
112 sm4e b0.4s, v24.4s; \
114 sm4e b0.4s, v25.4s; \
116 sm4e b0.4s, v26.4s; \
118 sm4e b0.4s, v27.4s; \
120 sm4e b0.4s, v28.4s; \
122 sm4e b0.4s, v29.4s; \
124 sm4e b0.4s, v30.4s; \
126 sm4e b0.4s, v31.4s; \
128 rev64 b0.4s, b0.4s; \
[all …]
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| D | aes-ce-core.S | 14 ld1 {v1.4s}, [x0], #16
21 ld1 {v3.4s}, [x0], #16
24 2: ld1 {v1.4s}, [x0], #16
27 3: ld1 {v2.4s}, [x0], #16
31 ld1 {v3.4s}, [x0], #16
42 ld1 {v1.4s}, [x0], #16
49 ld1 {v3.4s}, [x0], #16
52 2: ld1 {v1.4s}, [x0], #16
55 3: ld1 {v2.4s}, [x0], #16
59 ld1 {v3.4s}, [x0], #16
[all …]
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| /linux-6.14.4/arch/arm64/kernel/vdso/ |
| D | vgetrandom-chacha.S | 52 ld1 { copy1.4s, copy2.4s }, [x1]
54 ld1 { copy3.2s }, [x2]
56 movi one_v.2s, #1
57 uzp1 one_v.4s, one_v.4s, one_v.4s
76 add state0.4s, state0.4s, state1.4s
81 add state2.4s, state2.4s, state3.4s
83 shl state1.4s, tmp.4s, #12
84 sri state1.4s, tmp.4s, #20
87 add state0.4s, state0.4s, state1.4s
89 shl state3.4s, tmp.4s, #8
[all …]
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| /linux-6.14.4/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| D | tie.h | 7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
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| /linux-6.14.4/drivers/watchdog/ |
| D | sbc8360.c | 76 * MOV AX,000nH (set multiplier n, from 1-4)
95 * M | 1 2 3 4
97 * 0 | 0.5s 5s 50s 100s
98 * 1 | 1s 10s 100s 200s
99 * 2 | 1.5s 15s 150s 300s
100 * 3 | 2s 20s 200s 400s
101 * 4 | 2.5s 25s 250s 500s
102 * 5 | 3s 30s 300s 600s
103 * 6 | 3.5s 35s 350s 700s
104 * 7 | 4s 40s 400s 800s
[all …]
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| /linux-6.14.4/arch/xtensa/variants/test_kc705_be/include/variant/ |
| D | tie.h | 7 /* This header file describes this specific Xtensa processor's TIE extensions
68 #define XCHAL_NCP_SA_ALIGN 4
79 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
82 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
104 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
115 #define XCHAL_NCP_SA_LIST(s) \ argument
116 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
117 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
118 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
[all …]
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| /linux-6.14.4/arch/powerpc/crypto/ |
| D | chacha-p10le-8x.S | 17 # 4. c += d; b ^= c; b <<<= 7
24 # 4 blocks (a b c d)
198 vadduwm 0, 0, 4
224 vxor 4, 4, 8
235 vrlw 4, 4, 25 #
244 vadduwm 0, 0, 4
274 vxor 4, 4, 8
282 vrlw 4, 4, 28 #
298 vadduwm 3, 3, 4
325 vxor 4, 4, 9
[all …]
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| /linux-6.14.4/arch/xtensa/variants/dc232b/include/variant/ |
| D | tie.h | 2 * This header file describes this specific Xtensa processor's TIE extensions
46 #define XCHAL_NCP_SA_ALIGN 4
50 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
[all …]
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| /linux-6.14.4/tools/testing/selftests/cgroup/ |
| D | test_cpuset_prs.sh | 13 exit 4 # ksft_skip
28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
97 [[ $(echo $BOOT_ISOLCPUS | sed -e "s/[,-].*//") -le 8 ]] &&
182 # S<p> = use prefix in subtree_control
194 SETUP_A123_PARTITIONS="C1-3:P1:S+ C2-3:P1:S+ C3:P1"
198 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1"
200 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 "
201 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 "
202 " C0-1:S+ . . C2-3 . . . P1 0 "
203 " C0-1:P1 . . C2-3 S+ C1 . . 0 "
[all …]
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| /linux-6.14.4/arch/xtensa/variants/test_mmuhifi_c3/include/variant/ |
| D | tie.h | 2 * This header file describes this specific Xtensa processor's TIE extensions
45 #define XCHAL_NCP_SA_ALIGN 4
56 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
59 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
81 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
92 #define XCHAL_NCP_SA_LIST(s) \ argument
93 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
98 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
[all …]
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| /linux-6.14.4/arch/xtensa/variants/dc233c/include/variant/ |
| D | tie.h | 7 /* This header file describes this specific Xtensa processor's TIE extensions
65 #define XCHAL_NCP_SA_ALIGN 4
69 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
79 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
[all …]
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| /linux-6.14.4/Documentation/driver-api/mtd/ |
| D | spi-nor.rst | 14 flash's parameters and settings. If the flash defines the SFDP tables
15 it's likely that you won't need a flash entry at all, and instead
30 Do all the tests from below and paste them in the commit's comments
81 1S-1S-1S
85 1S-1S-1S (fast read)
89 1S-1S-2S
93 1S-2S-2S
95 mode cycles 4
97 1S-1S-4S
101 1S-4S-4S
[all …]
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| /linux-6.14.4/arch/mips/include/asm/octeon/ |
| D | cvmx-asxx-defs.h | 70 } s; member
83 } s; member
91 uint64_t txpsh:4;
92 uint64_t txpop:4;
93 uint64_t ovrflw:4;
95 uint64_t ovrflw:4;
96 uint64_t txpop:4;
97 uint64_t txpsh:4;
100 } s; member
125 uint64_t txpsh:4;
[all …]
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| D | cvmx-pko-defs.h | 99 } s; member
112 } s; member
129 } s; member
137 uint64_t back:4;
145 uint64_t back:4;
148 } s; member
159 } s; member
193 uint64_t back:4;
201 uint64_t back:4;
204 } s; member
[all …]
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| D | cvmx-lmcx-defs.h | 191 } s; member
216 } s; member
256 } s; member
282 } s; member
295 } s; member
306 } s; member
319 } s; member
352 } s; member
360 uint64_t nctl_csr:4;
361 uint64_t nctl_clk:4;
[all …]
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| /linux-6.14.4/lib/xz/ |
| D | xz_dec_bcj.c | 21 BCJ_X86 = 4, /* x86 or x86-64 */
68 * x86 1 4
69 * PowerPC 4 0
71 * ARM 4 0
73 * SPARC 4 0
89 static size_t bcj_x86(struct xz_dec_bcj *s, uint8_t *buf, size_t size) in bcj_x86() argument
98 uint32_t prev_mask = s->x86_prev_mask; in bcj_x86()
104 if (size <= 4) in bcj_x86()
107 size -= 4; in bcj_x86()
118 b = buf[i + 4 - mask_to_bit_num[prev_mask]]; in bcj_x86()
[all …]
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| /linux-6.14.4/drivers/comedi/drivers/ |
| D | adl_pci8164.c | 11 * Description: Driver for the Adlink PCI-8164 4 Axes Motion Control board
31 struct comedi_subdevice *s, in adl_pci8164_insn_read() argument
35 unsigned long offset = (unsigned long)s->private; in adl_pci8164_insn_read()
46 struct comedi_subdevice *s, in adl_pci8164_insn_write() argument
50 unsigned long offset = (unsigned long)s->private; in adl_pci8164_insn_write()
64 struct comedi_subdevice *s; in adl_pci8164_auto_attach() local
72 ret = comedi_alloc_subdevices(dev, 4); in adl_pci8164_auto_attach()
77 s = &dev->subdevices[0]; in adl_pci8164_auto_attach()
78 s->type = COMEDI_SUBD_PROC; in adl_pci8164_auto_attach()
79 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in adl_pci8164_auto_attach()
[all …]
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