Lines Matching +full:4 +full:s
2 * This header file describes this specific Xtensa processor's TIE extensions
46 #define XCHAL_NCP_SA_ALIGN 4
50 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
57 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
60 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
82 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
101 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
104 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
107 #define XCHAL_CP1_SA_LIST(s) /* empty */ argument
110 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
113 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
116 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
119 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
122 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
125 #define XCHAL_CP7_SA_LIST(s) /* empty */ argument