Lines Matching +full:4 +full:s
7 /* This header file describes this specific Xtensa processor's TIE extensions
65 #define XCHAL_NCP_SA_ALIGN 4
69 #define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */
76 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
79 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
101 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
123 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
126 #define XCHAL_CP1_SA_LIST(s) /* empty */ argument
129 #define XCHAL_CP2_SA_LIST(s) /* empty */ argument
132 #define XCHAL_CP3_SA_LIST(s) /* empty */ argument
135 #define XCHAL_CP4_SA_LIST(s) /* empty */ argument
138 #define XCHAL_CP5_SA_LIST(s) /* empty */ argument
141 #define XCHAL_CP6_SA_LIST(s) /* empty */ argument
144 #define XCHAL_CP7_SA_LIST(s) /* empty */ argument