Home
last modified time | relevance | path

Searched +full:16 +full:- +full:channel (Results 1 – 25 of 1047) sorted by relevance

12345678910>>...42

/linux-6.14.4/drivers/media/platform/nxp/imx8-isi/
Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
33 /* Channel Image Control Register */
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
87 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
[all …]
/linux-6.14.4/drivers/iio/dac/
Dad5446.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 * struct ad5446_state - driver instance specific data
53 * struct ad5446_chip_info - chip specific information
54 * @channel: channel spec for the DAC
60 struct iio_chan_spec channel; member
74 st->pwr_down_mode = mode + 1; in ad5446_set_powerdown_mode()
84 return st->pwr_down_mode - 1; in ad5446_get_powerdown_mode()
101 return sysfs_emit(buf, "%d\n", st->pwr_down); in ad5446_read_dac_powerdown()
119 mutex_lock(&st->lock); in ad5446_write_dac_powerdown()
120 st->pwr_down = powerdown; in ad5446_write_dac_powerdown()
[all …]
/linux-6.14.4/drivers/net/ethernet/microchip/
Dlan743x_main.h1 /* SPDX-License-Identifier: GPL-2.0+ */
77 #define DP_SEL_VHF_HASH_LEN (16)
130 #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16)
137 #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit))
141 #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit))
148 #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit))
152 #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) argument
153 #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) argument
154 #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) argument
157 #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) argument
[all …]
/linux-6.14.4/sound/pci/ca0106/
Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <[email protected]>
12 * Removed noise from Center/LFE channel when in Analog mode.
39 * 0.0.16
50 * Implement support for Line-in capture on SB Live 24bit.
65 /* CNL[1:0], ADDR[27:16] */
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
75 #define IPR_SPDIF_IN_USER 0x00004000 /* SPDIF input user data has 16 more bits */
76 #define IPR_SPDIF_OUT_USER 0x00002000 /* SPDIF output user data needs 16 more bits */
[all …]
/linux-6.14.4/drivers/gpu/drm/vmwgfx/
Dvmwgfx_msg.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
53 #define VMW_PORT_CMD_OPEN_CHANNEL (MSG_TYPE_OPEN << 16 | VMW_PORT_CMD_MSG)
54 #define VMW_PORT_CMD_CLOSE_CHANNEL (MSG_TYPE_CLOSE << 16 | VMW_PORT_CMD_MSG)
55 #define VMW_PORT_CMD_SENDSIZE (MSG_TYPE_SENDSIZE << 16 | VMW_PORT_CMD_MSG)
56 #define VMW_PORT_CMD_RECVSIZE (MSG_TYPE_RECVSIZE << 16 | VMW_PORT_CMD_MSG)
57 #define VMW_PORT_CMD_RECVSTATUS (MSG_TYPE_RECVSTATUS << 16 | VMW_PORT_CMD_MSG)
60 #define VMW_PORT_CMD_MKSGS_RESET (0 << 16 | VMW_PORT_CMD_MKS_GUEST_STATS)
61 #define VMW_PORT_CMD_MKSGS_ADD_PPN (1 << 16 | VMW_PORT_CMD_MKS_GUEST_STATS)
62 #define VMW_PORT_CMD_MKSGS_REMOVE_PPN (2 << 16 | VMW_PORT_CMD_MKS_GUEST_STATS)
[all …]
/linux-6.14.4/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <[email protected]>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
21 * 4 bytes for period_size << 16.
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
53 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
57 * [9:8] Playback input 0 channel select. 0 = Play output 0.
[all …]
/linux-6.14.4/Documentation/scsi/
Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iio/adc/
Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <[email protected]>
11 - Bjorn Andersson <[email protected]>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/linux-6.14.4/drivers/comedi/drivers/
Dcb_pcidda.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for the ComputerBoards / MeasurementComputing PCI-DDA series.
9 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 1997-8 David A. Schleef <[email protected]>
15 * Description: MeasurementComputing PCI-DDA series
16 * Devices: [Measurement Computing] PCI-DDA08/12 (pci-dda08/12),
17 * PCI-DDA04/12 (pci-dda04/12), PCI-DDA02/12 (pci-dda02/12),
18 * PCI-DDA08/16 (pci-dda08/16), PCI-DDA04/16 (pci-dda04/16),
19 * PCI-DDA02/16 (pci-dda02/16)
45 #define CB_DDA_DA_CTRL_DAC(x) ((x) << 2) /* Specify DAC channel */
[all …]
Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
94 #define PLX_MARBR_LTEN BIT(16)
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
102 #define PLX_MARBR_PRIO_DMA1 (BIT(19) * 2) /* DMA channel 1 has priority */
[all …]
/linux-6.14.4/drivers/net/wireless/mediatek/mt76/mt7915/
Deeprom.h1 /* SPDX-License-Identifier: ISC */
48 #define MT_EE_CAL_GROUP_SIZE_7915 (49 * MT_EE_CAL_UNIT + 16)
49 #define MT_EE_CAL_GROUP_SIZE_7916 (54 * MT_EE_CAL_UNIT + 16)
50 #define MT_EE_CAL_GROUP_SIZE_7975 (54 * MT_EE_CAL_UNIT + 16)
51 #define MT_EE_CAL_GROUP_SIZE_7976 (94 * MT_EE_CAL_UNIT + 16)
52 #define MT_EE_CAL_GROUP_SIZE_7916_6G (94 * MT_EE_CAL_UNIT + 16)
113 mt7915_get_channel_group_5g(int channel, bool is_7976) in mt7915_get_channel_group_5g() argument
116 if (channel <= 64) in mt7915_get_channel_group_5g()
118 if (channel <= 96) in mt7915_get_channel_group_5g()
120 if (channel <= 128) in mt7915_get_channel_group_5g()
[all …]
/linux-6.14.4/Documentation/sound/designs/
Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
[all …]
/linux-6.14.4/drivers/gpu/drm/sun4i/
Dsun8i_vi_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, in sun8i_vi_layer_update_alpha() argument
26 ch_base = sun8i_channel_base(mixer, channel); in sun8i_vi_layer_update_alpha()
28 if (mixer->cfg->is_de3) { in sun8i_vi_layer_update_alpha()
32 (plane->state->alpha >> 8); in sun8i_vi_layer_update_alpha()
34 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? in sun8i_vi_layer_update_alpha()
38 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_update_alpha()
42 } else if (mixer->cfg->vi_num == 1) { in sun8i_vi_layer_update_alpha()
43 regmap_update_bits(mixer->engine.regs, in sun8i_vi_layer_update_alpha()
47 (plane->state->alpha >> 8)); in sun8i_vi_layer_update_alpha()
[all …]
Dsun8i_ui_layer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Maxime Ripard <maxime.ripard@free-electrons.com>
27 static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, in sun8i_ui_layer_update_alpha() argument
32 ch_base = sun8i_channel_base(mixer, channel); in sun8i_ui_layer_update_alpha()
37 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA(plane->state->alpha >> 8); in sun8i_ui_layer_update_alpha()
39 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? in sun8i_ui_layer_update_alpha()
43 regmap_update_bits(mixer->engine.regs, in sun8i_ui_layer_update_alpha()
48 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, in sun8i_ui_layer_update_coord() argument
52 struct drm_plane_state *state = plane->state; in sun8i_ui_layer_update_coord()
58 DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n", in sun8i_ui_layer_update_coord()
[all …]
/linux-6.14.4/drivers/media/pci/tw5864/
Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
52 * [15:0] Two bit for each channel (channel 0 ~ 7). Each two bits are the buffer
53 * pointer for the last encoded frame of the corresponding channel.
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
120 /* [15:0] SEN_EN_CH[n] SENIF original frame capture enable for each channel */
[all …]
/linux-6.14.4/drivers/clk/bcm/
Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
49 .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
55 .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
61 .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
67 .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
73 .channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
75 .enable = ENABLE_VAL(0x0, 22, 16, 0),
[all …]
Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
87 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
[all …]
/linux-6.14.4/include/sound/
Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
27 /* MIDI 1.0 Channel Control (7bit) */
41 UMP_CC_GP_1 = 16,
134 u32 channel:4; member
140 u32 channel:4;
153 u32 channel:4; member
159 u32 channel:4;
172 u32 channel:4; member
178 u32 channel:4;
191 u32 channel:4; member
[all …]
/linux-6.14.4/sound/soc/sprd/
Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
57 /* Channel water mark definition */
58 #define MCDT_CH_FIFO_AE_SHIFT 16
59 #define MCDT_CH_FIFO_AE_MASK GENMASK(24, 16)
62 /* DMA channel select definition */
71 #define MCDT_DMA_CH4_SEL_MASK GENMASK(19, 16)
72 #define MCDT_DMA_CH4_SEL_SHIFT 16
73 #define MCDT_DAC_DMA_SHIFT 16
75 /* DMA channel ACK select definition */
[all …]
/linux-6.14.4/Documentation/fb/
Dviafb.rst6 --------
15 ---------------
29 color depth: 8 bpp, 16 bpp, 32 bpp supports.
34 ----------------------
41 #modprobe viafb viafb_mode=800x600 viafb_bpp=16 viafb_refresh=60
43 viafb_mode1=1024x768 viafb_bpp=16 viafb_refresh1=60
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
[all …]
/linux-6.14.4/sound/usb/caiaq/
Dcontrol.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 struct snd_usb_caiaqdev *cdev = caiaqdev(chip->card); in control_info()
25 int pos = kcontrol->private_value; in control_info()
29 uinfo->count = 1; in control_info()
32 switch (cdev->chip.usb_id) { in control_info()
37 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
38 uinfo->value.integer.min = 0; in control_info()
39 uinfo->value.integer.max = 2; in control_info()
54 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in control_info()
55 uinfo->value.integer.min = 0; in control_info()
[all …]
/linux-6.14.4/drivers/gpu/drm/renesas/rz-du/
Drzg2l_mipi_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define DSIDPHYCTRL0_CAL_EN_HSRX_OFS BIT(16)
27 #define DSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16)
33 #define DSIDPHYTIM2_TCLK_POST(x) ((x) << 16)
39 #define DSIDPHYTIM3_THS_EXIT(x) ((x) << 16)
43 /* --------------------------------------------------------*/
57 #define TXSETR_NUMLANECAP (0x3 << 16)
72 #define RSTCR_FCETXSTP BIT(16)
87 #define CLSTPTSETR_CLKBFHT(x) ((x) << 16)
99 /* Video-Input Channel 1 Set 0 Register */
[all …]
/linux-6.14.4/drivers/dma/ioat/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
18 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
20 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
27 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
30 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
32 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
33 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
34 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
36 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
[all …]
/linux-6.14.4/sound/pci/
Dad1889.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
[all …]
/linux-6.14.4/Documentation/core-api/
Ddma-isa-lpc.rst12 ------------------------
16 #include <linux/dma-mapping.h>
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
28 -----------------
37 The DMA-able address space is the lowest 16 MB of _physical_ memory.
39 or 128 KiB depending on which channel you use).
45 allocate the memory during boot-up it's a good idea to also pass
52 -------------------
66 --------
69 8-bit transfers and the upper four are for 16-bit transfers.
[all …]

12345678910>>...42