Lines Matching +full:16 +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
18 #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
20 #define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
27 #define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
30 #define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
32 #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
33 #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
34 #define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
36 #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
38 #define IOAT_VER_OFFSET 0x08 /* 8-bit */
44 #define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
46 #define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
50 #define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
56 #define IOAT_DMA_CAP_OFFSET 0x10 /* 32-bit */
72 #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
74 /* DMA Channel Registers */
75 #define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
89 #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
93 #define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
105 #define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
143 #define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
171 #define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
172 #define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
184 #define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
185 #define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
195 #define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
199 #define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
203 #define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
228 #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */