Lines Matching +full:16 +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
12 /* Channel Control Register */
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
33 /* Channel Image Control Register */
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
87 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)
113 /* Channel Output Buffer Control Register */
136 /* Channel Image Configuration */
138 #define CHNL_IMG_CFG_HEIGHT(n) ((n) << 16)
139 #define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
143 /* Channel Interrupt Enable Register */
153 /* Channel Status Register */
170 #define CHNL_STS_OFLW_Y_BUF BIT(16)
179 /* Channel Scale Factor Register */
181 #define CHNL_SCALE_FACTOR_Y_SCALE(n) ((n) << 16)
182 #define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16)
186 /* Channel Scale Offset Register */
188 #define CHNL_SCALE_OFFSET_Y_SCALE(n) ((n) << 16)
189 #define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)
193 /* Channel Crop Upper Left Corner Coordinate Register */
195 #define CHNL_CROP_ULC_X(n) ((n) << 16)
196 #define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)
200 /* Channel Crop Lower Right Corner Coordinate Register */
202 #define CHNL_CROP_LRC_X(n) ((n) << 16)
203 #define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)
207 /* Channel Color Space Conversion Coefficient Register 0 */
209 #define CHNL_CSC_COEFF0_A2(n) ((n) << 16)
210 #define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16)
214 /* Channel Color Space Conversion Coefficient Register 1 */
216 #define CHNL_CSC_COEFF1_B1(n) ((n) << 16)
217 #define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16)
221 /* Channel Color Space Conversion Coefficient Register 2 */
223 #define CHNL_CSC_COEFF2_B3(n) ((n) << 16)
224 #define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16)
228 /* Channel Color Space Conversion Coefficient Register 3 */
230 #define CHNL_CSC_COEFF3_C2(n) ((n) << 16)
231 #define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16)
235 /* Channel Color Space Conversion Coefficient Register 4 */
237 #define CHNL_CSC_COEFF4_D1(n) ((n) << 16)
238 #define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16)
242 /* Channel Color Space Conversion Coefficient Register 5 */
244 #define CHNL_CSC_COEFF5_D3(n) ((n) << 16)
245 #define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16)
249 /* Channel Alpha Value Register for ROI 0 */
253 #define CHNL_ROI_0_ALPHA_EN BIT(16)
255 /* Channel Upper Left Coordinate Register for ROI 0 */
257 #define CHNL_ROI_0_ULC_X(n) ((n) << 16)
258 #define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)
262 /* Channel Lower Right Coordinate Register for ROI 0 */
264 #define CHNL_ROI_0_LRC_X(n) ((n) << 16)
265 #define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)
269 /* Channel Alpha Value Register for ROI 1 */
273 #define CHNL_ROI_1_ALPHA_EN BIT(16)
275 /* Channel Upper Left Coordinate Register for ROI 1 */
277 #define CHNL_ROI_1_ULC_X(n) ((n) << 16)
278 #define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)
282 /* Channel Lower Right Coordinate Register for ROI 1 */
284 #define CHNL_ROI_1_LRC_X(n) ((n) << 16)
285 #define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)
289 /* Channel Alpha Value Register for ROI 2 */
293 #define CHNL_ROI_2_ALPHA_EN BIT(16)
295 /* Channel Upper Left Coordinate Register for ROI 2 */
297 #define CHNL_ROI_2_ULC_X(n) ((n) << 16)
298 #define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)
302 /* Channel Lower Right Coordinate Register for ROI 2 */
304 #define CHNL_ROI_2_LRC_X(n) ((n) << 16)
305 #define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16)
309 /* Channel Alpha Value Register for ROI 3 */
313 #define CHNL_ROI_3_ALPHA_EN BIT(16)
315 /* Channel Upper Left Coordinate Register for ROI 3 */
317 #define CHNL_ROI_3_ULC_X(n) ((n) << 16)
318 #define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16)
322 /* Channel Lower Right Coordinate Register for ROI 3 */
324 #define CHNL_ROI_3_LRC_X(n) ((n) << 16)
325 #define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16)
328 /* Channel RGB or Luma (Y) Output Buffer 1 Address */
331 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
334 /* Channel Chroma (V/Cr) Output Buffer 1 Address */
337 /* Channel Output Buffer Pitch */
342 /* Channel Input Buffer Address */
345 /* Channel Input Buffer Pitch */
347 #define CHNL_IN_BUF_PITCH_FRM_PITCH(n) ((n) << 16)
348 #define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16)
352 /* Channel Memory Read Control */
374 /* Channel RGB or Luma (Y) Output Buffer 2 Address */
377 /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
380 /* Channel Chroma (V/Cr) Output Buffer 2 Address */
383 /* Channel scale image config */
385 #define CHNL_SCL_IMG_CFG_HEIGHT(n) ((n) << 16)
386 #define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
390 /* Channel Flow Control Register */
394 #define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16)
397 /* Channel Output Y-Buffer 1 Extended Address Bits */
400 /* Channel Output U-Buffer 1 Extended Address Bits */
403 /* Channel Output V-Buffer 1 Extended Address Bits */
406 /* Channel Output Y-Buffer 2 Extended Address Bits */
409 /* Channel Output U-Buffer 2 Extended Address Bits */
412 /* Channel Output V-Buffer 2 Extended Address Bits */
415 /* Channel Input Buffer Extended Address Bits */