| /linux-6.14.4/Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| D | starfive,jh7110-stgcrg.yaml | 21 - description: Main Oscillator (24 MHz)
24 - description: USB (125 MHz)
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| /linux-6.14.4/drivers/media/tuners/ |
| D | qt1010_priv.h | 22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
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| /linux-6.14.4/Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
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| D | ti,dp83822.yaml | 87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
105 - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
106 clock frequency is 50-MHz and in RGMII Mode the clock frequency is
107 25-MHz.
109 - 'int-ref': Internal reference clock 25-MHz.
110 - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
113 - 'free-running': Free running clock 125-MHz.
114 - 'recovered': Recovered clock is a 125-MHz recovered clock from a
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| /linux-6.14.4/drivers/media/dvb-frontends/ |
| D | dvb-pll.c | 74 .min = 177 * MHz,
75 .max = 858 * MHz,
96 .min = 177 * MHz,
97 .max = 896 * MHz,
120 .min = 185 * MHz,
121 .max = 900 * MHz,
138 .min = 174 * MHz,
139 .max = 862 * MHz,
154 .min = 174 * MHz,
155 .max = 862 * MHz,
[all …]
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| D | stv0367.c | 67 u8 bw; /* channel width 6, 7 or 8 in MHz */
268 dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n"); in stv0367_pll_setup()
278 /* set internal freq to 53.125MHz */ in stv0367_pll_setup()
289 dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n"); in stv0367_pll_setup()
782 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
835 wd = stv0367ter_duration(mode, 125, 500, 250); in stv0367ter_lock_algo()
1064 /*set IIR filter once for 6,7 or 8MHz BW*/ in stv0367ter_algo()
1428 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR); in stv0367ter_snr_readreg()
1668 .frequency_min_hz = 47 * MHz,
1669 .frequency_max_hz = 862 * MHz,
[all …]
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| /linux-6.14.4/drivers/media/pci/cx18/ |
| D | cx18-firmware.c | 223 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in cx18_init_power()
239 * crystal value at all, it will assume 28.636360 MHz, the crystal in cx18_init_power()
242 * xtal_freq = 28.636360 MHz in cx18_init_power()
247 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_init_power()
254 /* the fast clock is at 200/245 MHz */ in cx18_init_power()
255 /* 1 * xtal_freq * 0x0d.f7df9b8 / 2 = 200 MHz: 400 MHz pre post-divide*/ in cx18_init_power()
256 /* 1 * xtal_freq * 0x11.1c71eb8 / 2 = 245 MHz: 490 MHz pre post-divide*/ in cx18_init_power()
265 /* set slow clock to 125/120 MHz */ in cx18_init_power()
266 /* xtal_freq * 0x0d.1861a20 / 3 = 125 MHz: 375 MHz before post-divide */ in cx18_init_power()
267 /* xtal_freq * 0x0c.92493f8 / 3 = 120 MHz: 360 MHz before post-divide */ in cx18_init_power()
[all …]
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| /linux-6.14.4/drivers/net/ethernet/intel/ice/ |
| D | ice_ptp_consts.h | 338 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
341 823437500, /* 823.4375 MHz PLL */
346 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
349 783360000, /* 783.36 MHz */
354 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
357 796875000, /* 796.875 MHz */
362 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
365 816000000, /* 816 MHz */
370 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
373 830078125, /* 830.78125 MHz */
[all …]
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| /linux-6.14.4/drivers/clk/spear/ |
| D | spear1340_clock.c | 164 /* PCLK 24MHz */
165 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
172 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
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| /linux-6.14.4/drivers/media/firewire/ |
| D | firedtv-fe.c | 173 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
174 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
175 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
193 fi->frequency_min_hz = 950 * MHz; in fdtv_frontend_init()
194 fi->frequency_max_hz = 2150 * MHz; in fdtv_frontend_init()
195 fi->frequency_stepsize_hz = 125 * kHz; in fdtv_frontend_init()
213 fi->frequency_min_hz = 47 * MHz; in fdtv_frontend_init()
214 fi->frequency_max_hz = 866 * MHz; in fdtv_frontend_init()
231 fi->frequency_min_hz = 49 * MHz; in fdtv_frontend_init()
232 fi->frequency_max_hz = 861 * MHz; in fdtv_frontend_init()
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| /linux-6.14.4/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-sti.c | 41 *| MII | n/a | 25Mhz |
44 *| GMII | 125Mhz | 25Mhz |
45 *| | clk-125/txclk | txclk |
47 *| RGMII | 125Mhz | 25Mhz |
48 *| | clk-125/txclk | clkgen |
51 *| RMII | n/a | 25Mhz |
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| D | dwmac-meson8b.c | 36 * cycle of the 125MHz RGMII TX clock):
359 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
361 * a register) based on the line-speed (125MHz for Gbit speeds, in meson8b_init_prg_eth()
362 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s). in meson8b_init_prg_eth()
364 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000); in meson8b_init_prg_eth()
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| D | dwmac-stm32.c | 72 *|PHY_MODE | Normal | PHY wo crystal| PHY wo crystal |No 125MHz from PHY|
73 *| | | 25MHz | 50MHz | |
307 /* Internal clock ETH_CLK of 50MHz from RCC is used */ in stm32mp2_configure_syscfg()
319 /* Internal clock ETH_CLK of 125MHz from RCC is used */ in stm32mp2_configure_syscfg()
454 /* Gigabit Ethernet 125MHz clock selection. */ in stm32mp1_parse_data()
457 /* Ethernet 50MHz RMII clock selection */ in stm32mp1_parse_data()
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| /linux-6.14.4/drivers/clk/sunxi/ |
| D | clk-a20-gmac.c | 36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
39 * The external 125 MHz reference is optional, i.e. GMAC can use its
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| /linux-6.14.4/Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 46 microchip,synclko-125:
49 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
55 microchip,synclko-125.
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| /linux-6.14.4/drivers/net/wireless/intel/iwlwifi/mvm/ |
| D | rfi.c | 11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
48 {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,},
52 /* frequency 5200MHz */
[all …]
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| /linux-6.14.4/drivers/clk/mvebu/ |
| D | dove.c | 26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
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| /linux-6.14.4/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
104 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
105 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
107 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
132 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
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| /linux-6.14.4/drivers/i2c/busses/ |
| D | i2c-stm32f4.c | 120 * @parent_rate: I2C clock parent rate in MHz
162 * a minimum value of 2 MHz and a maximum value of 46 MHz due in stm32f4_i2c_set_periph_clk_freq()
174 * frequency should be between a minimum value of 6 MHz and a in stm32f4_i2c_set_periph_clk_freq()
175 * maximum value of 46 MHz due to hardware limitation in stm32f4_i2c_set_periph_clk_freq()
202 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
203 * programmed with 0x9. (1000 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
208 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
209 * programmed with 0x3. (300 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
213 * is not higher than 46 MHz . As a result trise is at most 4 bits wide in stm32f4_i2c_set_rise_time()
237 * For example with parent rate = 2 MHz: in stm32f4_i2c_set_speed_mode()
[all …]
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| /linux-6.14.4/arch/arm/mach-omap2/ |
| D | timer.c | 53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
113 den = 125; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
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| /linux-6.14.4/drivers/clk/starfive/ |
| D | clk-starfive-jh7110-pll.c | 32 /* this driver expects a 24MHz input frequency from the oscillator */
158 * PLL0 frequency should be multiple of 125MHz (USB frequency).
163 .fbdiv = 125,
169 .fbdiv = 125,
181 .fbdiv = 125,
193 .fbdiv = 125,
211 .fbdiv = 125,
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| /linux-6.14.4/Documentation/devicetree/bindings/usb/ |
| D | dwc3-xilinx.yaml | 39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
|