67 	u8  bw; /* channel width 6, 7 or 8 in MHz */
268 			dprintk("STV0367 SetCLKgen for 58MHz IC and 27Mhz crystal\n");  in stv0367_pll_setup()
278 			/* set internal freq to 53.125MHz */  in stv0367_pll_setup()
289 			dprintk("FE_STV0367TER_SetCLKgen for 27Mhz\n");  in stv0367_pll_setup()
782 	wd = stv0367ter_duration(mode, 125, 500, 250);  in stv0367ter_lock_algo()
835 	wd = stv0367ter_duration(mode, 125, 500, 250);  in stv0367ter_lock_algo()
1064 		/*set IIR filter once for 6,7 or 8MHz BW*/  in stv0367ter_algo()
1428 			snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);  in stv0367ter_snr_readreg()
1668 		.frequency_min_hz	=  47 * MHz,
1669 		.frequency_max_hz	= 862 * MHz,
1989 			u32_tmp /= 125 ; /* 125 = 1000/2^3 */  in stv0367cab_set_srate()
2005 			u32_tmp /= 125 ; /* 125 = 1000/2**3 */  in stv0367cab_set_srate()
2020 			u32_tmp /= 125 ; /* 125 = 1000/2**3 */  in stv0367cab_set_srate()
2035 			u32_tmp /= 125 ; /* 125 = 1000/2**3 */  in stv0367cab_set_srate()
2091 		regsym *= 125 ;			/* 125 = 1000/2**3 */  in stv0367cab_GetSymbolRate()
2098 		regsym *= 125 ;			/* 125 = 1000/2**3*/  in stv0367cab_GetSymbolRate()
2105 		regsym *= 125 ;			/* 125 = 1000/2**3 */  in stv0367cab_GetSymbolRate()
2112 		regsym *= 125 ;			/* 125 = 1000/2**3 */  in stv0367cab_GetSymbolRate()
2837 		.frequency_min_hz =  47 * MHz,
2838 		.frequency_max_hz = 862 * MHz,
2929 	/* IC runs at 54 MHz with a 27 MHz crystal */  in stv0367ddb_setup_ter()
2960 	/* IC runs at 58 MHz with a 27 MHz crystal */  in stv0367ddb_setup_cab()
3183 	stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */  in stv0367ddb_init()
3203 	/* IC runs at 58 MHz with a 27 MHz crystal */  in stv0367ddb_init()
3243 		.frequency_min_hz	=  47 * MHz,
3244 		.frequency_max_hz	= 865 * MHz,