Lines Matching +full:125 +full:mhz
120 * @parent_rate: I2C clock parent rate in MHz
162 * a minimum value of 2 MHz and a maximum value of 46 MHz due in stm32f4_i2c_set_periph_clk_freq()
174 * frequency should be between a minimum value of 6 MHz and a in stm32f4_i2c_set_periph_clk_freq()
175 * maximum value of 46 MHz due to hardware limitation in stm32f4_i2c_set_periph_clk_freq()
202 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
203 * programmed with 0x9. (1000 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
208 * 0x08 so period = 125 ns therefore the TRISE[5:0] bits must be in stm32f4_i2c_set_rise_time()
209 * programmed with 0x3. (300 ns / 125 ns + 1) in stm32f4_i2c_set_rise_time()
213 * is not higher than 46 MHz . As a result trise is at most 4 bits wide in stm32f4_i2c_set_rise_time()
237 * For example with parent rate = 2 MHz: in stm32f4_i2c_set_speed_mode()
243 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()
256 * For example with parent rate = 6 MHz: in stm32f4_i2c_set_speed_mode()
263 * parent rate is not higher than 46 MHz . As a result val in stm32f4_i2c_set_speed_mode()