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/linux-6.14.4/Documentation/devicetree/bindings/phy/
Dphy-rockchip-naneng-combphy.yaml122 reg = <0xfdc50000 0x1000>;
127 reg = <0xfdc70000 0x1000>;
132 reg = <0xfe820000 0x100>;
/linux-6.14.4/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi11 cpu0_opp_table: opp-table-0 {
101 reg = <0 0xfc000000 0 0x1000>;
108 ports-implemented = <0x1>;
115 reg = <0x0 0xfdc70000 0x0 0x1000>;
120 reg = <0x0 0xfe190080 0x0 0x20>;
125 reg = <0x0 0xfe190100 0x0 0x20>;
130 reg = <0x0 0xfe190200 0x0 0x20>;
135 reg = <0x0 0xfdcb8000 0x0 0x10000>;
140 reg = <0x0 0xfe8c0000 0x0 0x20000>;
141 #phy-cells = <0>;
[all …]
/linux-6.14.4/drivers/phy/rockchip/
Dphy-rockchip-naneng-combphy.c3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG10 0x24
41 #define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
44 #define PHYREG11 0x28
45 #define PHYREG11_SU_TRIM_0_7 0xF0
[all …]