Lines Matching +full:0 +full:xfe820000
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG10 0x24
41 #define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
44 #define PHYREG11 0x28
45 #define PHYREG11_SU_TRIM_0_7 0xF0
47 #define PHYREG12 0x2C
50 #define PHYREG13 0x30
52 #define PHYREG13_RESISTER_SHIFT 0x4
56 #define PHYREG14 0x34
57 #define PHYREG14_CKRCV_AMP1 BIT(0)
59 #define PHYREG15 0x38
60 #define PHYREG15_CTLE_EN BIT(0)
65 #define PHYREG16 0x3C
66 #define PHYREG16_SSC_CNT_VALUE 0x5f
68 #define PHYREG17 0x40
70 #define PHYREG18 0x44
71 #define PHYREG18_PLL_LOOP 0x32
73 #define PHYREG21 0x50
74 #define PHYREG21_RX_SQUELCH_VAL 0x0D
76 #define PHYREG27 0x6C
77 #define PHYREG27_RX_TRIM_RK3588 0x4C
79 #define PHYREG30 0x74
81 #define PHYREG32 0x7C
85 #define PHYREG32_SSC_UPWARD 0
91 #define PHYREG33 0x80
248 return 0; in rockchip_combphy_init()
263 return 0; in rockchip_combphy_exit()
281 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
283 args->args[0], priv->type); in rockchip_combphy_xlate()
285 priv->type = args->args[0]; in rockchip_combphy_xlate()
299 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
334 return 0; in rockchip_combphy_parse_dt()
356 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
364 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
424 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
458 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
496 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3568_combphy_cfg()
558 return 0; in rk3568_combphy_cfg()
563 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
564 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
565 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
566 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
567 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
568 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
569 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
570 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
571 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
572 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
573 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
574 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
575 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
576 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
577 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
578 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
579 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
580 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
581 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
582 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
583 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
584 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
585 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
586 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
587 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
588 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
590 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
591 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
597 0xfe820000,
598 0xfe830000,
599 0xfe840000,
628 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3576_combphy_cfg()
687 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ in rk3576_combphy_cfg()
700 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
704 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
708 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
709 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
710 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
724 writel(0xc0, priv->mmio + PHYREG30); in rk3576_combphy_cfg()
732 writel(0x4c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
736 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
742 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
743 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
744 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
745 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
772 writel(0x0c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
776 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
782 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
783 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
784 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
785 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
796 writel(0x00, priv->mmio + PHYREG17); in rk3576_combphy_cfg()
800 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
804 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
809 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
810 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
811 writel(0x08, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
812 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
813 writel(0x40, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
822 return 0; in rk3576_combphy_cfg()
827 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
828 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
829 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
830 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
831 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
832 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
833 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
834 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
835 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
836 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
837 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
838 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
839 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
840 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
841 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
842 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
843 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
844 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
845 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
846 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
847 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
848 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
849 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
851 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
852 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
858 0x2b050000,
859 0x2b060000
892 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
924 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
949 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3588_combphy_cfg()
1008 return 0; in rk3588_combphy_cfg()
1013 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1014 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1015 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1016 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1017 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1018 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1019 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1020 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1021 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1022 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1023 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1024 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1025 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1026 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1027 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1028 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1029 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1030 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1031 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1032 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1034 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
1035 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
1036 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
1037 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
1043 0xfee00000,
1044 0xfee10000,
1045 0xfee20000,