1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip SoC Naneng Combo Phy
8
9maintainers:
10  - Heiko Stuebner <[email protected]>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,rk3568-naneng-combphy
16      - rockchip,rk3576-naneng-combphy
17      - rockchip,rk3588-naneng-combphy
18
19  reg:
20    maxItems: 1
21
22  clocks:
23    items:
24      - description: reference clock
25      - description: apb clock
26      - description: pipe clock
27
28  clock-names:
29    items:
30      - const: ref
31      - const: apb
32      - const: pipe
33
34  resets:
35    minItems: 1
36    maxItems: 2
37
38  reset-names:
39    minItems: 1
40    items:
41      - const: phy
42      - const: apb
43
44  rockchip,enable-ssc:
45    type: boolean
46    description:
47      The option SSC can be enabled for U3, SATA and PCIE.
48      Most commercially available platforms use SSC to reduce EMI.
49
50  rockchip,ext-refclk:
51    type: boolean
52    description:
53      Many PCIe connections, especially backplane connections,
54      require a synchronous reference clock between the two link partners.
55      To achieve this a common clock source, referred to as REFCLK in
56      the PCI Express Card Electromechanical Specification,
57      should be used by both ends of the PCIe link.
58      In PCIe mode one can choose to use an internal or an external reference
59      clock.
60      By default the internal clock is selected. The PCIe PHY provides a 100MHz
61      differential clock output(optional with SSC) for system applications.
62      When selecting this option an externally 100MHz differential
63      reference clock needs to be provided to the PCIe PHY.
64
65  rockchip,pipe-grf:
66    $ref: /schemas/types.yaml#/definitions/phandle
67    description:
68      Some additional phy settings are accessed through GRF regs.
69
70  rockchip,pipe-phy-grf:
71    $ref: /schemas/types.yaml#/definitions/phandle
72    description:
73      Some additional pipe settings are accessed through GRF regs.
74
75  "#phy-cells":
76    const: 1
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - clock-names
83  - resets
84  - rockchip,pipe-grf
85  - rockchip,pipe-phy-grf
86  - "#phy-cells"
87
88allOf:
89  - if:
90      properties:
91        compatible:
92          contains:
93            const: rockchip,rk3568-naneng-combphy
94    then:
95      properties:
96        resets:
97          maxItems: 1
98        reset-names:
99          maxItems: 1
100  - if:
101      properties:
102        compatible:
103          contains:
104            const: rockchip,rk3588-naneng-combphy
105    then:
106      properties:
107        resets:
108          minItems: 2
109        reset-names:
110          minItems: 2
111      required:
112        - reset-names
113
114additionalProperties: false
115
116examples:
117  - |
118    #include <dt-bindings/clock/rk3568-cru.h>
119
120    pipegrf: syscon@fdc50000 {
121      compatible = "rockchip,rk3568-pipe-grf", "syscon";
122      reg = <0xfdc50000 0x1000>;
123    };
124
125    pipe_phy_grf0: syscon@fdc70000 {
126      compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
127      reg = <0xfdc70000 0x1000>;
128    };
129
130    combphy0: phy@fe820000 {
131      compatible = "rockchip,rk3568-naneng-combphy";
132      reg = <0xfe820000 0x100>;
133      clocks = <&pmucru CLK_PCIEPHY0_REF>,
134               <&cru PCLK_PIPEPHY0>,
135               <&cru PCLK_PIPE>;
136      clock-names = "ref", "apb", "pipe";
137      assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
138      assigned-clock-rates = <100000000>;
139      resets = <&cru SRST_PIPEPHY0>;
140      rockchip,pipe-grf = <&pipegrf>;
141      rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
142      #phy-cells = <1>;
143    };
144