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/linux-6.14.4/Documentation/devicetree/bindings/media/
Dqcom,sc8280xp-camss.yaml127 port@0:
286 reg = <0 0x0ac5a000 0 0x2000>,
287 <0 0x0ac5c000 0 0x2000>,
288 <0 0x0ac65000 0 0x2000>,
289 <0 0x0ac67000 0 0x2000>,
290 <0 0x0acaf000 0 0x4000>,
291 <0 0x0acb3000 0 0x1000>,
292 <0 0x0acb6000 0 0x4000>,
293 <0 0x0acba000 0 0x1000>,
294 <0 0x0acbd000 0 0x4000>,
[all …]
Dqcom,sc7280-camss.yaml141 port@0:
145 Input port for receiving CSI data on CSIPHY 0.
270 reg = <0x0 0x0acb3000 0x0 0x1000>,
271 <0x0 0x0acba000 0x0 0x1000>,
272 <0x0 0x0acc1000 0x0 0x1000>,
273 <0x0 0x0acc8000 0x0 0x1000>,
274 <0x0 0x0accf000 0x0 0x1000>,
275 <0x0 0x0ace0000 0x0 0x2000>,
276 <0x0 0x0ace2000 0x0 0x2000>,
277 <0x0 0x0ace4000 0x0 0x2000>,
[all …]
/linux-6.14.4/drivers/gpu/drm/ci/xfails/
Dvkms-none-skips.txt7 # CPU: 0 PID: 2635 Comm: kworker/u8:13 Not tainted 6.9.0-rc7-g40935263a1fd #1
8 # Hardware name: ChromiumOS crosvm, BIOS 0
10 # RIP: 0010:compose_active_planes+0x1c7/0x4e0 [vkms]
11 …c9 0f 84 6a 01 00 00 8b 42 30 2b 42 28 41 39 c5 0f 8c 6f 01 00 00 49 83 c7 01 49 39 df 74 3b 4b 8b…
23 # ? __die+0x1e/0x60
24 # ? page_fault_oops+0x17b/0x490
25 # ? exc_page_fault+0x6d/0x230
26 # ? asm_exc_page_fault+0x26/0x30
27 # ? compose_active_planes+0x1c7/0x4e0 [vkms]
28 # ? compose_active_planes+0x2a3/0x4e0 [vkms]
[all …]
/linux-6.14.4/arch/sh/kernel/cpu/sh3/
Dsetup-sh770x.c24 UNUSED = 0,
36 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
37 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
38 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
39 INTC_VECT(RTC, 0x4c0),
40 INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500),
41 INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540),
42 INTC_VECT(WDT, 0x560),
43 INTC_VECT(REF, 0x580),
44 INTC_VECT(REF, 0x5a0),
[all …]
Dsetup-sh7720.c26 [0] = {
27 .start = 0xa413fec0,
28 .end = 0xa413fec0 + 0x28 - 1,
33 .start = evt2irq(0x480),
59 DEFINE_RES_MEM(0xa4430000, 0x100),
60 DEFINE_RES_IRQ(evt2irq(0xc00)),
65 .id = 0,
80 DEFINE_RES_MEM(0xa4438000, 0x100),
81 DEFINE_RES_IRQ(evt2irq(0xc20)),
95 [0] = {
[all …]
/linux-6.14.4/arch/powerpc/boot/dts/fsl/
Dpq3-rmu-0.dtsi2 * PQ3 RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
42 message-unit@0 {
44 reg = <0x0 0x100>;
46 53 2 0 0 /* msg1_tx_irq */
47 54 2 0 0>;/* msg1_rx_irq */
51 reg = <0x100 0x100>;
53 55 2 0 0 /* msg2_tx_irq */
54 56 2 0 0>;/* msg2_rx_irq */
[all …]
Dqoriq-rmu-0.dtsi2 * QorIQ RIO Message Unit device tree stub [ controller @ offset 0xd3000 ]
39 reg = <0xd3000 0x500>;
40 ranges = <0x0 0xd3000 0x500>;
42 message-unit@0 {
44 reg = <0x0 0x100>;
46 60 2 0 0 /* msg1_tx_irq */
47 61 2 0 0>;/* msg1_rx_irq */
51 reg = <0x100 0x100>;
53 62 2 0 0 /* msg2_tx_irq */
54 63 2 0 0>;/* msg2_rx_irq */
[all …]
/linux-6.14.4/arch/sh/kernel/cpu/sh4/
Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
Dprobe.c28 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff; in cpu_probe()
29 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; in cpu_probe()
56 if (((pvr >> 16) & 0xff) == 0x10) { in cpu_probe()
59 if ((cvr & 0x10000000) == 0) { in cpu_probe()
65 boot_cpu_data.cut_major = pvr & 0x7f; in cpu_probe()
76 if ((cvr & 0x20000000)) in cpu_probe()
80 pvr &= 0xffff; in cpu_probe()
87 case 0x205: in cpu_probe()
92 case 0x206: in cpu_probe()
97 case 0x1100: in cpu_probe()
[all …]
/linux-6.14.4/drivers/accel/habanalabs/include/goya/asic_reg/
Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/linux-6.14.4/drivers/mtd/parsers/
Dbcm63xxpart.c32 #define BCM963XX_CFE_MAGIC_OFFSET 0x4e0
33 #define BCM963XX_CFE_VERSION_OFFSET 0x570
34 #define BCM963XX_NVRAM_OFFSET 0x580
38 do { char *_str = (x); _str[sizeof(x) - 1] = 0; } while (0)
42 int ret = 0; in bcm63xx_detect_cfe()
72 return 0; in bcm63xx_read_nvram()
84 int nrparts = 3, curpart = 0; in bcm63xx_parse_cfe_nor_partitions()
102 parts[curpart].offset = 0; in bcm63xx_parse_cfe_nor_partitions()
117 for (i = 0; i < nrparts; i++) in bcm63xx_parse_cfe_nor_partitions()
/linux-6.14.4/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio-rmu.txt133 reg = <0xd3000 0x400>;
134 ranges = <0x0 0xd3000 0x400>;
135 fsl,liodn = <0xc8>;
137 message-unit@0 {
139 reg = <0x0 0x100>;
141 60 2 0 0 /* msg1_tx_irq */
142 61 2 0 0>;/* msg1_rx_irq */
146 reg = <0x100 0x100>;
148 62 2 0 0 /* msg2_tx_irq */
149 63 2 0 0>;/* msg2_rx_irq */
[all …]
/linux-6.14.4/drivers/soc/imx/
Dsoc-imx.c16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux-6.14.4/drivers/bcma/
Ddriver_pcie2.c19 #if 0
60 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844); in bcma_core_pcie2_set_ltr_vals()
61 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c); in bcma_core_pcie2_set_ltr_vals()
63 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848); in bcma_core_pcie2_set_ltr_vals()
64 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864); in bcma_core_pcie2_set_ltr_vals()
66 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C); in bcma_core_pcie2_set_ltr_vals()
67 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003); in bcma_core_pcie2_set_ltr_vals()
86 *si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); in bcma_core_pcie2_hw_ltr_war()
120 #if 0 in pciedev_crwlpciegen2()
123 #if 0 in pciedev_crwlpciegen2()
[all …]
/linux-6.14.4/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7770.c22 DEFINE_RES_MEM(0xff923000, 0x100),
23 DEFINE_RES_IRQ(evt2irq(0x9a0)),
28 .id = 0,
42 DEFINE_RES_MEM(0xff924000, 0x100),
43 DEFINE_RES_IRQ(evt2irq(0x9c0)),
62 DEFINE_RES_MEM(0xff925000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x9e0)),
82 DEFINE_RES_MEM(0xff926000, 0x100),
83 DEFINE_RES_IRQ(evt2irq(0xa00)),
102 DEFINE_RES_MEM(0xff927000, 0x100),
[all …]
/linux-6.14.4/drivers/net/ethernet/broadcom/asp2/
Dbcmasp_intf_defs.h6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]
/linux-6.14.4/drivers/net/ethernet/apple/
Dbmac.h17 #define XIFC 0x000 /* low-level interface control */
18 # define TxOutputEnable 0x0001 /* output driver enable */
19 # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
20 # define MIILoopback 0x0004 /* Loopback-mode MII enable */
21 # define MIILoopbackBits 0x0006
22 # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
23 # define SQETestEnable 0x0010 /* SQE test enable */
24 # define SQETimeWindow 0x03e0 /* SQE time window */
25 # define XIFLanceMode 0x0010 /* Lance mode enable */
26 # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/linux-6.14.4/drivers/media/platform/microchip/
Dmicrochip-isc-regs.h7 /* ISC Control Enable Register 0 */
8 #define ISC_CTRLEN 0x00000000
10 /* ISC Control Disable Register 0 */
11 #define ISC_CTRLDIS 0x00000004
13 /* ISC Control Status Register 0 */
14 #define ISC_CTRLSR 0x00000008
16 #define ISC_CTRL_CAPTURE BIT(0)
21 /* ISC Parallel Front End Configuration 0 Register */
22 #define ISC_PFE_CFG0 0x0000000c
24 #define ISC_PFE_CFG0_HPOL_LOW BIT(0)
[all …]

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