1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SC7280 CAMSS ISP
8
9maintainers:
10  - Azam Sadiq Pasha Kapatrala Syed <[email protected]>
11  - Hariram Purushothaman <[email protected]>
12
13description:
14  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
15
16properties:
17  compatible:
18    const: qcom,sc7280-camss
19
20  reg:
21    maxItems: 15
22
23  reg-names:
24    items:
25      - const: csid0
26      - const: csid1
27      - const: csid2
28      - const: csid_lite0
29      - const: csid_lite1
30      - const: csiphy0
31      - const: csiphy1
32      - const: csiphy2
33      - const: csiphy3
34      - const: csiphy4
35      - const: vfe0
36      - const: vfe1
37      - const: vfe2
38      - const: vfe_lite0
39      - const: vfe_lite1
40
41  clocks:
42    maxItems: 33
43
44  clock-names:
45    items:
46      - const: camnoc_axi
47      - const: cpas_ahb
48      - const: csiphy0
49      - const: csiphy0_timer
50      - const: csiphy1
51      - const: csiphy1_timer
52      - const: csiphy2
53      - const: csiphy2_timer
54      - const: csiphy3
55      - const: csiphy3_timer
56      - const: csiphy4
57      - const: csiphy4_timer
58      - const: gcc_camera_ahb
59      - const: gcc_cam_hf_axi
60      - const: icp_ahb
61      - const: vfe0
62      - const: vfe0_axi
63      - const: vfe0_cphy_rx
64      - const: vfe0_csid
65      - const: vfe1
66      - const: vfe1_axi
67      - const: vfe1_cphy_rx
68      - const: vfe1_csid
69      - const: vfe2
70      - const: vfe2_axi
71      - const: vfe2_cphy_rx
72      - const: vfe2_csid
73      - const: vfe_lite0
74      - const: vfe_lite0_cphy_rx
75      - const: vfe_lite0_csid
76      - const: vfe_lite1
77      - const: vfe_lite1_cphy_rx
78      - const: vfe_lite1_csid
79
80  interrupts:
81    maxItems: 15
82
83  interrupt-names:
84    items:
85      - const: csid0
86      - const: csid1
87      - const: csid2
88      - const: csid_lite0
89      - const: csid_lite1
90      - const: csiphy0
91      - const: csiphy1
92      - const: csiphy2
93      - const: csiphy3
94      - const: csiphy4
95      - const: vfe0
96      - const: vfe1
97      - const: vfe2
98      - const: vfe_lite0
99      - const: vfe_lite1
100
101  interconnects:
102    maxItems: 2
103
104  interconnect-names:
105    items:
106      - const: ahb
107      - const: hf_0
108
109  iommus:
110    maxItems: 1
111
112  power-domains:
113    items:
114      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
115      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
116      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
117      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
118
119  power-domain-names:
120    items:
121      - const: ife0
122      - const: ife1
123      - const: ife2
124      - const: top
125
126  vdda-phy-supply:
127    description:
128      Phandle to a regulator supply to PHY core block.
129
130  vdda-pll-supply:
131    description:
132      Phandle to 1.8V regulator supply to PHY refclk pll block.
133
134  ports:
135    $ref: /schemas/graph.yaml#/properties/ports
136
137    description:
138      CSI input ports.
139
140    properties:
141      port@0:
142        $ref: /schemas/graph.yaml#/$defs/port-base
143        unevaluatedProperties: false
144        description:
145          Input port for receiving CSI data on CSIPHY 0.
146
147        properties:
148          endpoint:
149            $ref: video-interfaces.yaml#
150            unevaluatedProperties: false
151
152            properties:
153              data-lanes:
154                minItems: 1
155                maxItems: 4
156
157            required:
158              - data-lanes
159
160      port@1:
161        $ref: /schemas/graph.yaml#/$defs/port-base
162        unevaluatedProperties: false
163        description:
164          Input port for receiving CSI data on CSIPHY 1.
165
166        properties:
167          endpoint:
168            $ref: video-interfaces.yaml#
169            unevaluatedProperties: false
170
171            properties:
172              data-lanes:
173                minItems: 1
174                maxItems: 4
175
176            required:
177              - data-lanes
178
179      port@2:
180        $ref: /schemas/graph.yaml#/$defs/port-base
181        unevaluatedProperties: false
182        description:
183          Input port for receiving CSI data on CSIPHY 2.
184
185        properties:
186          endpoint:
187            $ref: video-interfaces.yaml#
188            unevaluatedProperties: false
189
190            properties:
191              data-lanes:
192                minItems: 1
193                maxItems: 4
194
195            required:
196              - data-lanes
197
198      port@3:
199        $ref: /schemas/graph.yaml#/$defs/port-base
200        unevaluatedProperties: false
201        description:
202          Input port for receiving CSI data on CSIPHY 3.
203
204        properties:
205          endpoint:
206            $ref: video-interfaces.yaml#
207            unevaluatedProperties: false
208
209            properties:
210              data-lanes:
211                minItems: 1
212                maxItems: 4
213
214            required:
215              - data-lanes
216
217      port@4:
218        $ref: /schemas/graph.yaml#/$defs/port-base
219        unevaluatedProperties: false
220        description:
221          Input port for receiving CSI data on CSIPHY 4.
222
223        properties:
224          endpoint:
225            $ref: video-interfaces.yaml#
226            unevaluatedProperties: false
227
228            properties:
229              data-lanes:
230                minItems: 1
231                maxItems: 4
232
233            required:
234              - data-lanes
235
236required:
237  - compatible
238  - reg
239  - reg-names
240  - clocks
241  - clock-names
242  - interrupts
243  - interrupt-names
244  - interconnects
245  - interconnect-names
246  - iommus
247  - power-domains
248  - power-domain-names
249  - vdda-phy-supply
250  - vdda-pll-supply
251
252additionalProperties: false
253
254examples:
255  - |
256    #include <dt-bindings/clock/qcom,camcc-sc7280.h>
257    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
258    #include <dt-bindings/interconnect/qcom,sc7280.h>
259    #include <dt-bindings/interconnect/qcom,icc.h>
260    #include <dt-bindings/interrupt-controller/arm-gic.h>
261    #include <dt-bindings/power/qcom-rpmpd.h>
262
263    soc {
264        #address-cells = <2>;
265        #size-cells = <2>;
266
267        isp@acb3000 {
268            compatible = "qcom,sc7280-camss";
269
270            reg = <0x0 0x0acb3000 0x0 0x1000>,
271                  <0x0 0x0acba000 0x0 0x1000>,
272                  <0x0 0x0acc1000 0x0 0x1000>,
273                  <0x0 0x0acc8000 0x0 0x1000>,
274                  <0x0 0x0accf000 0x0 0x1000>,
275                  <0x0 0x0ace0000 0x0 0x2000>,
276                  <0x0 0x0ace2000 0x0 0x2000>,
277                  <0x0 0x0ace4000 0x0 0x2000>,
278                  <0x0 0x0ace6000 0x0 0x2000>,
279                  <0x0 0x0ace8000 0x0 0x2000>,
280                  <0x0 0x0acaf000 0x0 0x4000>,
281                  <0x0 0x0acb6000 0x0 0x4000>,
282                  <0x0 0x0acbd000 0x0 0x4000>,
283                  <0x0 0x0acc4000 0x0 0x4000>,
284                  <0x0 0x0accb000 0x0 0x4000>;
285            reg-names = "csid0",
286                        "csid1",
287                        "csid2",
288                        "csid_lite0",
289                        "csid_lite1",
290                        "csiphy0",
291                        "csiphy1",
292                        "csiphy2",
293                        "csiphy3",
294                        "csiphy4",
295                        "vfe0",
296                        "vfe1",
297                        "vfe2",
298                        "vfe_lite0",
299                        "vfe_lite1";
300
301            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
302                     <&camcc CAM_CC_CPAS_AHB_CLK>,
303                     <&camcc CAM_CC_CSIPHY0_CLK>,
304                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
305                     <&camcc CAM_CC_CSIPHY1_CLK>,
306                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
307                     <&camcc CAM_CC_CSIPHY2_CLK>,
308                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
309                     <&camcc CAM_CC_CSIPHY3_CLK>,
310                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
311                     <&camcc CAM_CC_CSIPHY4_CLK>,
312                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
313                     <&gcc GCC_CAMERA_AHB_CLK>,
314                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
315                     <&camcc CAM_CC_ICP_AHB_CLK>,
316                     <&camcc CAM_CC_IFE_0_CLK>,
317                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
318                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
319                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
320                     <&camcc CAM_CC_IFE_1_CLK>,
321                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
322                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
323                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
324                     <&camcc CAM_CC_IFE_2_CLK>,
325                     <&camcc CAM_CC_IFE_2_AXI_CLK>,
326                     <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
327                     <&camcc CAM_CC_IFE_2_CSID_CLK>,
328                     <&camcc CAM_CC_IFE_LITE_0_CLK>,
329                     <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
330                     <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
331                     <&camcc CAM_CC_IFE_LITE_1_CLK>,
332                     <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
333                     <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
334            clock-names = "camnoc_axi",
335                          "cpas_ahb",
336                          "csiphy0",
337                          "csiphy0_timer",
338                          "csiphy1",
339                          "csiphy1_timer",
340                          "csiphy2",
341                          "csiphy2_timer",
342                          "csiphy3",
343                          "csiphy3_timer",
344                          "csiphy4",
345                          "csiphy4_timer",
346                          "gcc_camera_ahb",
347                          "gcc_cam_hf_axi",
348                          "icp_ahb",
349                          "vfe0",
350                          "vfe0_axi",
351                          "vfe0_cphy_rx",
352                          "vfe0_csid",
353                          "vfe1",
354                          "vfe1_axi",
355                          "vfe1_cphy_rx",
356                          "vfe1_csid",
357                          "vfe2",
358                          "vfe2_axi",
359                          "vfe2_cphy_rx",
360                          "vfe2_csid",
361                          "vfe_lite0",
362                          "vfe_lite0_cphy_rx",
363                          "vfe_lite0_csid",
364                          "vfe_lite1",
365                          "vfe_lite1_cphy_rx",
366                          "vfe_lite1_csid";
367
368            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
369                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
370                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
371                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
372                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
373                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
374                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
375                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
376                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
377                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
378                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
379                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
380                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
381                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
382                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
383            interrupt-names = "csid0",
384                              "csid1",
385                              "csid2",
386                              "csid_lite0",
387                              "csid_lite1",
388                              "csiphy0",
389                              "csiphy1",
390                              "csiphy2",
391                              "csiphy3",
392                              "csiphy4",
393                              "vfe0",
394                              "vfe1",
395                              "vfe2",
396                              "vfe_lite0",
397                              "vfe_lite1";
398
399            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
400                             &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
401                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
402                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
403            interconnect-names = "ahb",
404                                 "hf_0";
405
406            iommus = <&apps_smmu 0x800 0x4e0>;
407
408            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
409                            <&camcc CAM_CC_IFE_1_GDSC>,
410                            <&camcc CAM_CC_IFE_2_GDSC>,
411                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
412            power-domain-names = "ife0",
413                                 "ife1",
414                                 "ife2",
415                                 "top";
416
417            vdda-phy-supply = <&vreg_l10c_0p88>;
418            vdda-pll-supply = <&vreg_l6b_1p2>;
419
420            ports {
421                #address-cells = <1>;
422                #size-cells = <0>;
423            };
424        };
425    };
426