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/linux-6.14.4/drivers/reset/
Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/linux-6.14.4/drivers/usb/serial/
Dpl2303.h6 #define BENQ_VENDOR_ID 0x04a5
7 #define BENQ_PRODUCT_ID_S81 0x4027
9 #define PL2303_VENDOR_ID 0x067b
10 #define PL2303_PRODUCT_ID 0x2303
11 #define PL2303_PRODUCT_ID_TB 0x2304
12 #define PL2303_PRODUCT_ID_GC 0x23a3
13 #define PL2303_PRODUCT_ID_GB 0x23b3
14 #define PL2303_PRODUCT_ID_GT 0x23c3
15 #define PL2303_PRODUCT_ID_GL 0x23d3
16 #define PL2303_PRODUCT_ID_GE 0x23e3
[all …]
/linux-6.14.4/drivers/net/wireless/realtek/rtw89/
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/linux-6.14.4/sound/soc/codecs/
Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/msm/
Dqcom,qcm2290-dpu.yaml61 reg = <0x05e01000 0x8f000>,
62 <0x05eb0000 0x2008>;
76 interrupts = <0>;
80 #size-cells = <0>;
82 port@0 {
83 reg = <0>;
Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
Dqcom,sm8150-dpu.yaml56 reg = <0x0ae01000 0x8f000>,
57 <0x0aeb0000 0x2008>;
73 interrupts = <0>;
77 #size-cells = <0>;
79 port@0 {
80 reg = <0>;
Dqcom,sm6150-dpu.yaml52 reg = <0x0ae01000 0x8f000>,
53 <0x0aeb0000 0x2008>;
69 interrupts = <0>;
73 #size-cells = <0>;
75 port@0 {
76 reg = <0>;
Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
Dqcom,sc7280-dpu.yaml71 reg = <0x0ae01000 0x8f000>,
72 <0x0aeb0000 0x2008>;
90 interrupts = <0>;
96 #size-cells = <0>;
98 port@0 {
99 reg = <0>;
Dqcom,sm8650-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
85 interrupts = <0>;
89 #size-cells = <0>;
91 port@0 {
92 reg = <0>;
Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
Dqcom,sc8280xp-mdss.yaml35 "^display-controller@[0-9a-f]+$":
43 "^displayport-controller@[0-9a-f]+$":
65 reg = <0x0ae00000 0x1000>;
83 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
84 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
87 iommus = <&apps_smmu 0x1000 0x402>;
95 reg = <0x0ae01000 0x8f000>,
96 <0x0aeb0000 0x2008>;
119 interrupts = <0>;
123 #size-cells = <0>;
[all …]
/linux-6.14.4/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-fsd.c23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]
/linux-6.14.4/drivers/media/platform/qcom/venus/
Dhfi_venus_io.h9 #define VBIF_BASE 0x80000
11 #define VBIF_AXI_HALT_CTRL0 0x208
12 #define VBIF_AXI_HALT_CTRL1 0x20c
14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0)
15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0)
18 #define CPU_BASE 0xc0000
20 #define CPU_CS_BASE (CPU_BASE + 0x12000)
21 #define CPU_IC_BASE (CPU_BASE + 0x1f000)
22 #define CPU_BASE_V6 0xa0000
24 #define CPU_IC_BASE_V6 (CPU_BASE_V6 + 0x138)
[all …]
/linux-6.14.4/drivers/dma/xilinx/
Dxdma-regs.h32 #define XDMA_DESC_MAGIC 0xad4bUL
34 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
35 #define XDMA_DESC_STOPPED BIT(0)
75 #define XDMA_CHAN_IDENTIFIER 0x0
76 #define XDMA_CHAN_CONTROL 0x4
77 #define XDMA_CHAN_CONTROL_W1S 0x8
78 #define XDMA_CHAN_CONTROL_W1C 0xc
79 #define XDMA_CHAN_STATUS 0x40
80 #define XDMA_CHAN_STATUS_RC 0x44
81 #define XDMA_CHAN_COMPLETED_DESC 0x48
[all …]
/linux-6.14.4/drivers/net/wwan/t7xx/
Dt7xx_port.h34 #define PORT_CH_ID_MASK GENMASK(7, 0)
37 * The channel number consists of peer_id(15:12) , channel_id(11:0)
39 * 0:reserved, 1: to AP, 2: to MD
43 PORT_CH_AP_CONTROL_RX = 0x1000,
44 PORT_CH_AP_CONTROL_TX = 0x1001,
45 PORT_CH_AP_ADB_RX = 0x100a,
46 PORT_CH_AP_ADB_TX = 0x100b,
49 PORT_CH_CONTROL_RX = 0x2000,
50 PORT_CH_CONTROL_TX = 0x2001,
51 PORT_CH_UART1_RX = 0x2006, /* META */
[all …]
/linux-6.14.4/drivers/media/platform/samsung/s5p-mfc/
Dregs-mfc.h20 #define S5P_FIMV_START_ADDR 0x0000
21 #define S5P_FIMV_END_ADDR 0xe008
23 #define S5P_FIMV_SW_RESET 0x0000
24 #define S5P_FIMV_RISC_HOST_INT 0x0008
27 #define S5P_FIMV_HOST2RISC_CMD 0x0030
28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034
29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038
30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c
31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040
34 #define S5P_FIMV_RISC2HOST_CMD 0x0044
[all …]
/linux-6.14.4/drivers/clk/qcom/
Ddispcc-qcm2290.c42 .l = 0x28,
43 .vco_val = 0x2 << 20,
45 .main_output_mask = BIT(0),
46 .config_ctl_val = 0x4001055B,
50 .offset = 0x0,
67 { P_BI_TCXO, 0 },
77 { P_BI_TCXO, 0 },
85 { P_BI_TCXO_AO, 0 },
95 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
[all …]
/linux-6.14.4/drivers/net/ethernet/marvell/octeontx2/af/
Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
[all …]
/linux-6.14.4/include/uapi/linux/
Dmedia-bus-format.h16 * These bus formats uniquely identify data formats on the data bus. Format 0
35 #define MEDIA_BUS_FMT_FIXED 0x0001
37 /* RGB - next is 0x1028 */
38 #define MEDIA_BUS_FMT_RGB444_1X12 0x1016
39 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
40 #define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
41 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
42 #define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
43 #define MEDIA_BUS_FMT_RGB565_1X16 0x1017
44 #define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
[all …]
/linux-6.14.4/include/linux/mfd/mt6359p/
Dregisters.h9 #define MT6359P_CHIP_VER 0x5930
12 #define MT6359P_HWCID 0x8
13 #define MT6359P_TOP_TRAP 0x50
14 #define MT6359P_TOP_TMA_KEY 0x3a8
15 #define MT6359P_BUCK_VCORE_ELR_NUM 0x152a
16 #define MT6359P_BUCK_VCORE_ELR0 0x152c
17 #define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa
18 #define MT6359P_BUCK_VGPU11_ELR0 0x15b4
19 #define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44
20 #define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46
[all …]

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