1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Ltd.
5 */
6
7 #include <linux/err.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13
14 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
15
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
18 #include "clk-rcg.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "common.h"
22 #include "gdsc.h"
23 #include "reset.h"
24
25 enum {
26 P_BI_TCXO,
27 P_BI_TCXO_AO,
28 P_DISP_CC_PLL0_OUT_MAIN,
29 P_DSI0_PHY_PLL_OUT_BYTECLK,
30 P_DSI0_PHY_PLL_OUT_DSICLK,
31 P_GPLL0_OUT_DIV,
32 P_GPLL0_OUT_MAIN,
33 P_SLEEP_CLK,
34 };
35
36 static const struct pll_vco spark_vco[] = {
37 { 500000000, 1000000000, 2 },
38 };
39
40 /* 768MHz configuration */
41 static const struct alpha_pll_config disp_cc_pll0_config = {
42 .l = 0x28,
43 .vco_val = 0x2 << 20,
44 .vco_mask = GENMASK(21, 20),
45 .main_output_mask = BIT(0),
46 .config_ctl_val = 0x4001055B,
47 };
48
49 static struct clk_alpha_pll disp_cc_pll0 = {
50 .offset = 0x0,
51 .vco_table = spark_vco,
52 .num_vco = ARRAY_SIZE(spark_vco),
53 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
54 .clkr = {
55 .hw.init = &(struct clk_init_data){
56 .name = "disp_cc_pll0",
57 .parent_data = &(const struct clk_parent_data){
58 .fw_name = "bi_tcxo",
59 },
60 .num_parents = 1,
61 .ops = &clk_alpha_pll_ops,
62 },
63 },
64 };
65
66 static const struct parent_map disp_cc_parent_map_0[] = {
67 { P_BI_TCXO, 0 },
68 { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
69 };
70
71 static const struct clk_parent_data disp_cc_parent_data_0[] = {
72 { .fw_name = "bi_tcxo" },
73 { .fw_name = "dsi0_phy_pll_out_byteclk" },
74 };
75
76 static const struct parent_map disp_cc_parent_map_1[] = {
77 { P_BI_TCXO, 0 },
78 };
79
80 static const struct clk_parent_data disp_cc_parent_data_1[] = {
81 { .fw_name = "bi_tcxo" },
82 };
83
84 static const struct parent_map disp_cc_parent_map_2[] = {
85 { P_BI_TCXO_AO, 0 },
86 { P_GPLL0_OUT_DIV, 4 },
87 };
88
89 static const struct clk_parent_data disp_cc_parent_data_2[] = {
90 { .fw_name = "bi_tcxo_ao" },
91 { .fw_name = "gcc_disp_gpll0_div_clk_src" },
92 };
93
94 static const struct parent_map disp_cc_parent_map_3[] = {
95 { P_BI_TCXO, 0 },
96 { P_DISP_CC_PLL0_OUT_MAIN, 1 },
97 { P_GPLL0_OUT_MAIN, 4 },
98 };
99
100 static const struct clk_parent_data disp_cc_parent_data_3[] = {
101 { .fw_name = "bi_tcxo" },
102 { .hw = &disp_cc_pll0.clkr.hw },
103 { .fw_name = "gcc_disp_gpll0_clk_src" },
104 };
105
106 static const struct parent_map disp_cc_parent_map_4[] = {
107 { P_BI_TCXO, 0 },
108 { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
109 };
110
111 static const struct clk_parent_data disp_cc_parent_data_4[] = {
112 { .fw_name = "bi_tcxo" },
113 { .fw_name = "dsi0_phy_pll_out_dsiclk" },
114 };
115
116 static const struct parent_map disp_cc_parent_map_5[] = {
117 { P_SLEEP_CLK, 0 },
118 };
119
120 static const struct clk_parent_data disp_cc_parent_data_5[] = {
121 { .fw_name = "sleep_clk" },
122 };
123
124 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
125 .cmd_rcgr = 0x20a4,
126 .mnd_width = 0,
127 .hid_width = 5,
128 .parent_map = disp_cc_parent_map_0,
129 .clkr.hw.init = &(struct clk_init_data){
130 .name = "disp_cc_mdss_byte0_clk_src",
131 .parent_data = disp_cc_parent_data_0,
132 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
133 /* For set_rate and set_parent to succeed, parent(s) must be enabled */
134 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
135 .ops = &clk_byte2_ops,
136 },
137 };
138
139 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
140 .reg = 0x20bc,
141 .shift = 0,
142 .width = 2,
143 .clkr.hw.init = &(struct clk_init_data) {
144 .name = "disp_cc_mdss_byte0_div_clk_src",
145 .parent_hws = (const struct clk_hw*[]){
146 &disp_cc_mdss_byte0_clk_src.clkr.hw,
147 },
148 .num_parents = 1,
149 .ops = &clk_regmap_div_ops,
150 },
151 };
152
153 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
154 F(19200000, P_BI_TCXO_AO, 1, 0, 0),
155 F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
156 F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
157 { }
158 };
159
160 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
161 .cmd_rcgr = 0x2154,
162 .mnd_width = 0,
163 .hid_width = 5,
164 .parent_map = disp_cc_parent_map_2,
165 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
166 .clkr.hw.init = &(struct clk_init_data){
167 .name = "disp_cc_mdss_ahb_clk_src",
168 .parent_data = disp_cc_parent_data_2,
169 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
170 .ops = &clk_rcg2_shared_ops,
171 },
172 };
173
174 static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = {
175 F(19200000, P_BI_TCXO, 1, 0, 0),
176 { }
177 };
178
179 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
180 .cmd_rcgr = 0x20c0,
181 .mnd_width = 0,
182 .hid_width = 5,
183 .parent_map = disp_cc_parent_map_0,
184 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
185 .clkr.hw.init = &(struct clk_init_data){
186 .name = "disp_cc_mdss_esc0_clk_src",
187 .parent_data = disp_cc_parent_data_0,
188 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
189 .ops = &clk_rcg2_ops,
190 },
191 };
192
193 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
194 F(19200000, P_BI_TCXO, 1, 0, 0),
195 F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
196 F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
197 F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
198 F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
199 { }
200 };
201
202 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
203 .cmd_rcgr = 0x2074,
204 .mnd_width = 0,
205 .hid_width = 5,
206 .parent_map = disp_cc_parent_map_3,
207 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
208 .clkr.hw.init = &(struct clk_init_data){
209 .name = "disp_cc_mdss_mdp_clk_src",
210 .parent_data = disp_cc_parent_data_3,
211 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
212 .flags = CLK_SET_RATE_PARENT,
213 .ops = &clk_rcg2_shared_ops,
214 },
215 };
216
217 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
218 .cmd_rcgr = 0x205c,
219 .mnd_width = 8,
220 .hid_width = 5,
221 .parent_map = disp_cc_parent_map_4,
222 .clkr.hw.init = &(struct clk_init_data){
223 .name = "disp_cc_mdss_pclk0_clk_src",
224 .parent_data = disp_cc_parent_data_4,
225 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
226 /* For set_rate and set_parent to succeed, parent(s) must be enabled */
227 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
228 .ops = &clk_pixel_ops,
229 },
230 };
231
232 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
233 .cmd_rcgr = 0x208c,
234 .mnd_width = 0,
235 .hid_width = 5,
236 .parent_map = disp_cc_parent_map_1,
237 .freq_tbl = ftbl_disp_cc_mdss_esc0_clk_src,
238 .clkr.hw.init = &(struct clk_init_data){
239 .name = "disp_cc_mdss_vsync_clk_src",
240 .parent_data = disp_cc_parent_data_1,
241 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
242 .flags = CLK_SET_RATE_PARENT,
243 .ops = &clk_rcg2_shared_ops,
244 },
245 };
246
247 static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
248 F(32764, P_SLEEP_CLK, 1, 0, 0),
249 { }
250 };
251
252 static struct clk_rcg2 disp_cc_sleep_clk_src = {
253 .cmd_rcgr = 0x6050,
254 .mnd_width = 0,
255 .hid_width = 5,
256 .parent_map = disp_cc_parent_map_5,
257 .freq_tbl = ftbl_disp_cc_sleep_clk_src,
258 .clkr.hw.init = &(struct clk_init_data){
259 .name = "disp_cc_sleep_clk_src",
260 .parent_data = disp_cc_parent_data_5,
261 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
262 .ops = &clk_rcg2_ops,
263 },
264 };
265
266 static struct clk_branch disp_cc_mdss_ahb_clk = {
267 .halt_reg = 0x2044,
268 .halt_check = BRANCH_HALT,
269 .clkr = {
270 .enable_reg = 0x2044,
271 .enable_mask = BIT(0),
272 .hw.init = &(struct clk_init_data){
273 .name = "disp_cc_mdss_ahb_clk",
274 .parent_hws = (const struct clk_hw*[]){
275 &disp_cc_mdss_ahb_clk_src.clkr.hw,
276 },
277 .num_parents = 1,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_branch2_ops,
280 },
281 },
282 };
283
284 static struct clk_branch disp_cc_mdss_byte0_clk = {
285 .halt_reg = 0x201c,
286 .halt_check = BRANCH_HALT,
287 .clkr = {
288 .enable_reg = 0x201c,
289 .enable_mask = BIT(0),
290 .hw.init = &(struct clk_init_data){
291 .name = "disp_cc_mdss_byte0_clk",
292 .parent_hws = (const struct clk_hw*[]){
293 &disp_cc_mdss_byte0_clk_src.clkr.hw,
294 },
295 .num_parents = 1,
296 .flags = CLK_SET_RATE_PARENT,
297 .ops = &clk_branch2_ops,
298 },
299 },
300 };
301
302 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
303 .halt_reg = 0x2020,
304 .halt_check = BRANCH_HALT,
305 .clkr = {
306 .enable_reg = 0x2020,
307 .enable_mask = BIT(0),
308 .hw.init = &(struct clk_init_data){
309 .name = "disp_cc_mdss_byte0_intf_clk",
310 .parent_hws = (const struct clk_hw*[]){
311 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
312 },
313 .num_parents = 1,
314 .flags = CLK_SET_RATE_PARENT,
315 .ops = &clk_branch2_ops,
316 },
317 },
318 };
319
320 static struct clk_branch disp_cc_mdss_esc0_clk = {
321 .halt_reg = 0x2024,
322 .halt_check = BRANCH_HALT,
323 .clkr = {
324 .enable_reg = 0x2024,
325 .enable_mask = BIT(0),
326 .hw.init = &(struct clk_init_data){
327 .name = "disp_cc_mdss_esc0_clk",
328 .parent_hws = (const struct clk_hw*[]){
329 &disp_cc_mdss_esc0_clk_src.clkr.hw,
330 },
331 .num_parents = 1,
332 .flags = CLK_SET_RATE_PARENT,
333 .ops = &clk_branch2_ops,
334 },
335 },
336 };
337
338 static struct clk_branch disp_cc_mdss_mdp_clk = {
339 .halt_reg = 0x2008,
340 .halt_check = BRANCH_HALT,
341 .clkr = {
342 .enable_reg = 0x2008,
343 .enable_mask = BIT(0),
344 .hw.init = &(struct clk_init_data){
345 .name = "disp_cc_mdss_mdp_clk",
346 .parent_hws = (const struct clk_hw*[]){
347 &disp_cc_mdss_mdp_clk_src.clkr.hw,
348 },
349 .num_parents = 1,
350 .flags = CLK_SET_RATE_PARENT,
351 .ops = &clk_branch2_ops,
352 },
353 },
354 };
355
356 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
357 .halt_reg = 0x2010,
358 .halt_check = BRANCH_HALT_VOTED,
359 .clkr = {
360 .enable_reg = 0x2010,
361 .enable_mask = BIT(0),
362 .hw.init = &(struct clk_init_data){
363 .name = "disp_cc_mdss_mdp_lut_clk",
364 .parent_hws = (const struct clk_hw*[]){
365 &disp_cc_mdss_mdp_clk_src.clkr.hw,
366 },
367 .num_parents = 1,
368 .flags = CLK_SET_RATE_PARENT,
369 .ops = &clk_branch2_ops,
370 },
371 },
372 };
373
374 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
375 .halt_reg = 0x4004,
376 .halt_check = BRANCH_HALT_VOTED,
377 .clkr = {
378 .enable_reg = 0x4004,
379 .enable_mask = BIT(0),
380 .hw.init = &(struct clk_init_data){
381 .name = "disp_cc_mdss_non_gdsc_ahb_clk",
382 .parent_hws = (const struct clk_hw*[]){
383 &disp_cc_mdss_ahb_clk_src.clkr.hw,
384 },
385 .num_parents = 1,
386 .flags = CLK_SET_RATE_PARENT,
387 .ops = &clk_branch2_ops,
388 },
389 },
390 };
391
392 static struct clk_branch disp_cc_mdss_pclk0_clk = {
393 .halt_reg = 0x2004,
394 .halt_check = BRANCH_HALT,
395 .clkr = {
396 .enable_reg = 0x2004,
397 .enable_mask = BIT(0),
398 .hw.init = &(struct clk_init_data){
399 .name = "disp_cc_mdss_pclk0_clk",
400 .parent_hws = (const struct clk_hw*[]){
401 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
402 },
403 .num_parents = 1,
404 .flags = CLK_SET_RATE_PARENT,
405 .ops = &clk_branch2_ops,
406 },
407 },
408 };
409
410 static struct clk_branch disp_cc_mdss_vsync_clk = {
411 .halt_reg = 0x2018,
412 .halt_check = BRANCH_HALT,
413 .clkr = {
414 .enable_reg = 0x2018,
415 .enable_mask = BIT(0),
416 .hw.init = &(struct clk_init_data){
417 .name = "disp_cc_mdss_vsync_clk",
418 .parent_hws = (const struct clk_hw*[]){
419 &disp_cc_mdss_vsync_clk_src.clkr.hw,
420 },
421 .num_parents = 1,
422 .flags = CLK_SET_RATE_PARENT,
423 .ops = &clk_branch2_ops,
424 },
425 },
426 };
427
428 static struct clk_branch disp_cc_sleep_clk = {
429 .halt_reg = 0x6068,
430 .halt_check = BRANCH_HALT,
431 .clkr = {
432 .enable_reg = 0x6068,
433 .enable_mask = BIT(0),
434 .hw.init = &(struct clk_init_data){
435 .name = "disp_cc_sleep_clk",
436 .parent_hws = (const struct clk_hw*[]){
437 &disp_cc_sleep_clk_src.clkr.hw,
438 },
439 .num_parents = 1,
440 .flags = CLK_SET_RATE_PARENT,
441 .ops = &clk_branch2_ops,
442 },
443 },
444 };
445
446 static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
447 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
448 };
449
450 static struct gdsc mdss_gdsc = {
451 .gdscr = 0x3000,
452 .pd = {
453 .name = "mdss_gdsc",
454 },
455 .pwrsts = PWRSTS_OFF_ON,
456 .flags = HW_CTRL,
457 };
458
459 static struct gdsc *disp_cc_qcm2290_gdscs[] = {
460 [MDSS_GDSC] = &mdss_gdsc,
461 };
462
463 static struct clk_regmap *disp_cc_qcm2290_clocks[] = {
464 [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
465 [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
466 [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
467 [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
468 [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
469 [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
470 [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
471 [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
472 [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
473 [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
474 [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
475 [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
476 [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
477 [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
478 [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
479 [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
480 [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
481 [DISP_CC_SLEEP_CLK] = &disp_cc_sleep_clk.clkr,
482 [DISP_CC_SLEEP_CLK_SRC] = &disp_cc_sleep_clk_src.clkr,
483 };
484
485 static const struct regmap_config disp_cc_qcm2290_regmap_config = {
486 .reg_bits = 32,
487 .reg_stride = 4,
488 .val_bits = 32,
489 .max_register = 0x10000,
490 .fast_io = true,
491 };
492
493 static const struct qcom_cc_desc disp_cc_qcm2290_desc = {
494 .config = &disp_cc_qcm2290_regmap_config,
495 .clks = disp_cc_qcm2290_clocks,
496 .num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks),
497 .gdscs = disp_cc_qcm2290_gdscs,
498 .num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs),
499 .resets = disp_cc_qcm2290_resets,
500 .num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets),
501 };
502
503 static const struct of_device_id disp_cc_qcm2290_match_table[] = {
504 { .compatible = "qcom,qcm2290-dispcc" },
505 { }
506 };
507 MODULE_DEVICE_TABLE(of, disp_cc_qcm2290_match_table);
508
disp_cc_qcm2290_probe(struct platform_device * pdev)509 static int disp_cc_qcm2290_probe(struct platform_device *pdev)
510 {
511 struct regmap *regmap;
512 int ret;
513
514 regmap = qcom_cc_map(pdev, &disp_cc_qcm2290_desc);
515 if (IS_ERR(regmap))
516 return PTR_ERR(regmap);
517
518 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
519
520 /* Keep some clocks always-on */
521 qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */
522
523 ret = qcom_cc_really_probe(&pdev->dev, &disp_cc_qcm2290_desc, regmap);
524 if (ret) {
525 dev_err(&pdev->dev, "Failed to register DISP CC clocks\n");
526 return ret;
527 }
528
529 return ret;
530 }
531
532 static struct platform_driver disp_cc_qcm2290_driver = {
533 .probe = disp_cc_qcm2290_probe,
534 .driver = {
535 .name = "dispcc-qcm2290",
536 .of_match_table = disp_cc_qcm2290_match_table,
537 },
538 };
539
540 module_platform_driver(disp_cc_qcm2290_driver);
541
542 MODULE_DESCRIPTION("QTI DISP_CC qcm2290 Driver");
543 MODULE_LICENSE("GPL v2");
544