Lines Matching +full:0 +full:x2008
42 .l = 0x28,
43 .vco_val = 0x2 << 20,
45 .main_output_mask = BIT(0),
46 .config_ctl_val = 0x4001055B,
50 .offset = 0x0,
67 { P_BI_TCXO, 0 },
77 { P_BI_TCXO, 0 },
85 { P_BI_TCXO_AO, 0 },
95 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
117 { P_SLEEP_CLK, 0 },
125 .cmd_rcgr = 0x20a4,
126 .mnd_width = 0,
140 .reg = 0x20bc,
141 .shift = 0,
154 F(19200000, P_BI_TCXO_AO, 1, 0, 0),
155 F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0),
156 F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0),
161 .cmd_rcgr = 0x2154,
162 .mnd_width = 0,
175 F(19200000, P_BI_TCXO, 1, 0, 0),
180 .cmd_rcgr = 0x20c0,
181 .mnd_width = 0,
194 F(19200000, P_BI_TCXO, 1, 0, 0),
195 F(192000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
196 F(256000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
197 F(307200000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
198 F(384000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
203 .cmd_rcgr = 0x2074,
204 .mnd_width = 0,
218 .cmd_rcgr = 0x205c,
233 .cmd_rcgr = 0x208c,
234 .mnd_width = 0,
248 F(32764, P_SLEEP_CLK, 1, 0, 0),
253 .cmd_rcgr = 0x6050,
254 .mnd_width = 0,
267 .halt_reg = 0x2044,
270 .enable_reg = 0x2044,
271 .enable_mask = BIT(0),
285 .halt_reg = 0x201c,
288 .enable_reg = 0x201c,
289 .enable_mask = BIT(0),
303 .halt_reg = 0x2020,
306 .enable_reg = 0x2020,
307 .enable_mask = BIT(0),
321 .halt_reg = 0x2024,
324 .enable_reg = 0x2024,
325 .enable_mask = BIT(0),
339 .halt_reg = 0x2008,
342 .enable_reg = 0x2008,
343 .enable_mask = BIT(0),
357 .halt_reg = 0x2010,
360 .enable_reg = 0x2010,
361 .enable_mask = BIT(0),
375 .halt_reg = 0x4004,
378 .enable_reg = 0x4004,
379 .enable_mask = BIT(0),
393 .halt_reg = 0x2004,
396 .enable_reg = 0x2004,
397 .enable_mask = BIT(0),
411 .halt_reg = 0x2018,
414 .enable_reg = 0x2018,
415 .enable_mask = BIT(0),
429 .halt_reg = 0x6068,
432 .enable_reg = 0x6068,
433 .enable_mask = BIT(0),
447 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
451 .gdscr = 0x3000,
489 .max_register = 0x10000,
521 qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ in disp_cc_qcm2290_probe()