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/linux-6.14.4/drivers/gpu/drm/radeon/
Drv770_smc.c34 #define FIRST_SMC_INT_VECT_REG 0xFFD8
35 #define FIRST_INT_VECT_S19 0xFFC0
38 0x08, 0x10, 0x08, 0x10,
39 0x08, 0x10, 0x08, 0x10,
40 0x08, 0x10, 0x08, 0x10,
41 0x08, 0x10, 0x08, 0x10,
42 0x08, 0x10, 0x08, 0x10,
43 0x08, 0x10, 0x08, 0x10,
44 0x08, 0x10, 0x08, 0x10,
45 0x08, 0x10, 0x08, 0x10,
[all …]
/linux-6.14.4/arch/arm/boot/dts/rockchip/
Drk3288-veyron-jerry.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "../cros-ec-sbs.dtsi"
14 compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
15 "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
16 "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
17 "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
18 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
19 "google,veyron-jerry-rev3", "google,veyron-jerry",
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dpcs/
Ddpcs_3_0_0_sh_mask.h1 // SPDX-License-Identifier: MIT
14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
[all …]
Ddpcs_3_0_3_sh_mask.h1 // SPDX-License-Identifier: MIT
14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
[all …]
/linux-6.14.4/arch/x86/pci/
Dce4100.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * This provides access methods for PCI registers that mis-behave on
13 * bridge device is the only device on bus zero (0) that requires any
40 #define SIZE_TO_MASK(size) (~(size - 1))
44 {0, SIZE_TO_MASK(size)} },
51 pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4, in reg_init()
52 &reg->sim_reg.value); in reg_init()
57 *value = reg->sim_reg.value; in reg_read()
62 reg->sim_reg.value = (value & reg->sim_reg.mask) | in reg_write()
63 (reg->sim_reg.value & ~reg->sim_reg.mask); in reg_write()
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_5_0_sh_mask.h1 /* SPDX-License-Identifier: MIT */
27 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
28 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
29 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
30 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
31 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
32 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
33 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
34 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
35 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
[all …]
Ddcn_3_5_1_sh_mask.h1 /* SPDX-License-Identifier: MIT */
6 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
7 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
8 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
9 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
10 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
11 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
12 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
13 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
14 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
[all …]
Ddcn_3_1_4_sh_mask.h1 /* SPDX-License-Identifier: MIT */
31 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
32 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
34 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
35 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
36 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
37 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
39 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
40 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
41 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
[all …]
Ddcn_3_0_0_sh_mask.h1 // SPDX-License-Identifier: MIT
8 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
9 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
10 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
11 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
13 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
14 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
15 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
16 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
18 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
[all …]
Ddcn_3_0_3_sh_mask.h1 // SPDX-License-Identifier: MIT
14 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
15 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
16 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
17 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
19 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
20 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
21 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
22 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
24 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
[all …]
/linux-6.14.4/drivers/clk/bcm/
Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
33 .aon = AON_VAL(0x0, 1, 15, 12),
34 .reset = RESET_VAL(0x4, 2, 1),
35 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
36 .ndiv_int = REG_VAL(0x8, 4, 10),
37 .pdiv = REG_VAL(0x8, 0, 4),
38 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
[all …]
Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
37 .aon = AON_VAL(0x0, 5, 1, 0),
38 .reset = RESET_VAL(0x0, 12, 11),
39 .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
40 .sw_ctrl = SW_CTRL_VAL(0x10, 31),
41 .ndiv_int = REG_VAL(0x10, 20, 10),
42 .ndiv_frac = REG_VAL(0x10, 0, 20),
[all …]
/linux-6.14.4/include/linux/regulator/
Dpca9450.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 PCA9450_TYPE_PCA9450A = 0,
18 PCA9450_BUCK1 = 0,
33 PCA9450_DVS_LEVEL_RUN = 0,
38 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
40 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
41 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
43 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
44 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
[all …]
/linux-6.14.4/arch/arm/crypto/
Dchacha-scalar-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
14 * (x8, x9) to the stack and swap them out with (x10, x11). This adds one
24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such
37 X8_X10 .req r8 // shared by x8 and x10
41 X14 .req r12
78 // drot == 32 - 16 == 16
85 // brot == 32 - 12 == 20
92 // drot == 32 - 8 == 24
99 // brot == 32 - 7 == 25
109 // save (x8, x9); restore (x10, x11)
[all …]
/linux-6.14.4/crypto/
Dtestmgr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (c) 2002 Jean-Francois Dive <[email protected]>
11 * Updated RFC4106 AES-GCM testing. Some test vectors were taken from
13 * gcm/gcm-test-vectors.tar.gz
34 * @ksize: Length of @key in bytes (0 if no key)
54 * @iv: Pointer to IV. If NULL, an all-zeroes IV is used.
82 * @iv: Pointer to IV. If NULL, an all-zeroes IV is used.
89 * tested, and it is expected to fail with either -EBADMSG or
101 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
103 * for decrypt() to return besides -EBADMSG.
[all …]
/linux-6.14.4/drivers/video/fbdev/via/
Dhw.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 #include <linux/via-core.h>
13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
[all …]
/linux-6.14.4/drivers/video/fbdev/sis/
Dinit.h6 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
23 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
[all …]
/linux-6.14.4/drivers/net/ethernet/realtek/
Dr8169_phy_config.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <[email protected]>
23 int oldpage = phy_select_page(phydev, 0x0007); in r8168d_modify_extpage()
25 __phy_write(phydev, 0x1e, extpage); in r8168d_modify_extpage()
28 phy_restore_page(phydev, oldpage, 0); in r8168d_modify_extpage()
34 int oldpage = phy_select_page(phydev, 0x0005); in r8168d_phy_param()
36 __phy_write(phydev, 0x05, parm); in r8168d_phy_param()
37 __phy_modify(phydev, 0x06, mask, val); in r8168d_phy_param()
39 phy_restore_page(phydev, oldpage, 0); in r8168d_phy_param()
45 int oldpage = phy_select_page(phydev, 0x0a43); in r8168g_phy_param()
[all …]
/linux-6.14.4/drivers/media/usb/gspca/
Dsonixb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2011 Jean-François Moine <http://moinejf.free.fr>
14 0x10 high nibble red gain low nibble blue gain
15 0x11 low nibble green gain
17 0x05 red gain 0-127
18 0x06 blue gain 0-127
19 0x07 green gain 0-127
21 0x08-0x0f i2c / 3wire registers
22 0x12 hstart
23 0x13 vstart
[all …]
/linux-6.14.4/drivers/phy/starfive/
Dphy-jh7110-dphy-tx.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/phy/phy-mipi-dphy.h>
26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
[all …]
/linux-6.14.4/arch/x86/crypto/
Dchacha-ssse3-x86_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ChaCha 256-bit cipher algorithm, x64 SSSE3 functions
13 ROT8: .octa 0x0e0d0c0f0a09080b0605040702010003
16 ROT16: .octa 0x0d0c0f0e09080b0a0504070601000302
19 CTRINC: .octa 0x00000003000000020000000100000000
24 * chacha_permute - permute one block
26 * Permute one 64-byte block where the state matrix is in %xmm0-%xmm3. This
28 * shuffling to rearrange the words after each round. 8/16-bit word rotation is
29 * done with the slightly better performing SSSE3 byte shuffling, 7/12-bit word
34 * Clobbers: %r8d, %xmm4-%xmm7
[all …]
/linux-6.14.4/drivers/pinctrl/bcm/
Dpinctrl-cygnus-mux.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014-2017 Broadcom
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
158 CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
159 CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
160 CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
161 CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
162 CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
163 CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
[all …]
/linux-6.14.4/drivers/net/wireless/realtek/rtl8xxxu/
D8192c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RTL8XXXU mac80211 USB driver - 8188c/8188r/8192c specific subdriver
5 * Copyright (c) 2014 - 2017 Jes Sorensen <[email protected]>
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
21 .reg_0e00 = 0x07090c0c,
22 .reg_0e04 = 0x01020405,
23 .reg_0e08 = 0x00000000,
24 .reg_086c = 0x00000000,
26 .reg_0e10 = 0x0b0c0c0e,
27 .reg_0e14 = 0x01030506,
[all …]
/linux-6.14.4/drivers/media/tuners/
Dfc2580_priv.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-subdev.h>
23 {0x00, 0x00},
24 {0x12, 0x86},
25 {0x14, 0x5c},
26 {0x16, 0x3c},
27 {0x1f, 0xd2},
28 {0x09, 0xd7},
29 {0x0b, 0xd5},
[all …]
/linux-6.14.4/include/linux/mfd/syscon/
Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
27 #define ATMEL_SMC_NWE_SHIFT 0
32 #define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
[all …]

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