1 // SPDX-License-Identifier: GPL-2.0-only
10  * This provides access methods for PCI registers that mis-behave on
13  * bridge device is the only device on bus zero (0) that requires any
40 #define SIZE_TO_MASK(size) (~(size - 1))
44 	{0, SIZE_TO_MASK(size)} },
51 	pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,  in reg_init()
52 			      &reg->sim_reg.value);  in reg_init()
57 	*value = reg->sim_reg.value;  in reg_read()
62 	reg->sim_reg.value = (value & reg->sim_reg.mask) |  in reg_write()
63 		(reg->sim_reg.value & ~reg->sim_reg.mask);  in reg_write()
68 	pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,  in sata_reg_init()
69 			      &reg->sim_reg.value);  in sata_reg_init()
70 	reg->sim_reg.value += 0x400;  in sata_reg_init()
76 	if (*value != reg->sim_reg.mask)  in ehci_reg_read()
77 		*value |= 0x100;  in ehci_reg_read()
82 	reg->sim_reg.value = 0x01060100;  in sata_revid_init()
83 	reg->sim_reg.mask = 0;  in sata_revid_init()
93 	/* force interrupt pin value to 0 */  in reg_noirq_read()
94 	*value = reg->sim_reg.value & 0xfff00ff;  in reg_noirq_read()
98 	DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
99 	DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
100 	DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
101 	DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
102 	DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
103 	DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
104 	DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
105 	DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
106 	DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
107 	DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
108 	DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
109 	DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
110 	DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
111 	DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
112 	DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
113 	DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
114 	DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
115 	DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
116 	DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
117 	DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
118 	DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
119 	DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
120 	DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
121 	DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
122 	DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
123 	DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
124 	DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
125 	DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
126 	DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
127 	DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
128 	DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
129 	DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
130 	DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
131 	DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
132 	DEFINE_REG(14, 0, 0x8,  0, sata_revid_init, sata_revid_read, 0)
133 	DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
134 	DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
135 	DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
136 	DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
137 	DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
138 	DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
139 	DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
140 	DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
141 	DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
142 	DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
143 	DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
144 	DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
145 	DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
146 	DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
147 	DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
154 	for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {  in init_sim_regs()
165 	mask = 0xFFFFFFFF >> ((4 - len) * 8);  in extract_bytes()
172 	int retval = 0;  in bridge_read()
180 		*value = 0;  in bridge_read()
188 			*value = 0x00010100;  in bridge_read()
198 		pci_direct_conf1.read(0, 0, devfn,  in bridge_read()
201 		av_bridge_limit = av_bridge_base + (512*MB - 1);  in bridge_read()
203 		av_bridge_limit &= 0xFFF0;  in bridge_read()
206 		av_bridge_base &= 0xFFF0;  in bridge_read()
219 		*value = 0xFFF0;  in bridge_read()
222 		*value = 0x0;  in bridge_read()
226 		*value = 0xF0;  in bridge_read()
229 		*value = 0;  in bridge_read()
242 	for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {  in ce4100_bus1_read()
251 			return 0;  in ce4100_bus1_read()
254 	return -1;  in ce4100_bus1_read()
263 		return 0;  in ce4100_conf_read()
265 	if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&  in ce4100_conf_read()
267 		return 0;  in ce4100_conf_read()
277 	for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {  in ce4100_bus1_write()
285 			return 0;  in ce4100_bus1_write()
288 	return -1;  in ce4100_bus1_write()
297 		return 0;  in ce4100_conf_write()
300 	if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&  in ce4100_conf_write()
302 		return 0;  in ce4100_conf_write()