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/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dimx8qm-ss-hsio.dtsi9 ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
10 <0x40000000 0x0 0x60000000 0x10000000>,
11 <0x80000000 0x0 0x70000000 0x10000000>;
17 reg = <0x5f000000 0x10000>,
18 <0x4ff00000 0x80000>;
20 ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
21 <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
31 bus-range = <0x00 0xff>;
33 interrupt-map = <0 0 0 1 &gic 0 73 4>,
34 <0 0 0 2 &gic 0 74 4>,
[all …]
Dimx8-ss-hsio.dtsi11 #clock-cells = <0>;
18 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #clock-cells = <0>;
46 ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
47 <0x80000000 0x0 0x70000000 0x10000000>;
50 dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
54 reg = <0x5f010000 0x10000>,
55 <0x8ff00000 0x80000>;
[all …]
/linux-6.14.4/drivers/net/wireless/realtek/rtw89/
Drtw8852bt_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x0000000f, 0x4),
9 RTW89_DECL_RFK_WM(0x32a8, 0x0000000f, 0x4),
10 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0x5555),
11 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0x5555),
12 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16),
13 RTW89_DECL_RFK_WM(0x0304, 0x000000ff, 0x19),
14 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041),
15 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x2041),
16 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041),
17 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3),
[all …]
Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dmsm8992-lg-h815.dts26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
39 reg = <0x0 0x06000000 0x0 0x00001000>;
45 reg = <0x0 0x0ff00000 0x0 0x00100000>;
46 console-size = <0x20000>;
47 pmsg-size = <0x20000>;
48 record-size = <0x10000>;
49 ecc-size = <0x10>;
53 reg = <0x0 0x03400000 0x0 0x00c00000>;
[all …]
/linux-6.14.4/drivers/cpufreq/
Dpowernow-k8.h43 #define CPUID_XFAM 0x0ff00000 /* extended family */
44 #define CPUID_XFAM_K8 0
45 #define CPUID_XMOD 0x000f0000 /* extended model */
46 #define CPUID_XMOD_REV_MASK 0x000c0000
47 #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
48 #define CPUID_USE_XFAM_XMOD 0x00000f00
49 #define CPUID_GET_MAX_CAPABILITIES 0x80000000
50 #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
[all …]
/linux-6.14.4/include/uapi/linux/
Din6.h83 #define IPV6_FL_A_GET 0
92 #define IPV6_FL_S_NONE 0
107 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
108 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
111 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
112 #define IPV6_PRIORITY_FILLER 0x0100
113 #define IPV6_PRIORITY_UNATTENDED 0x0200
114 #define IPV6_PRIORITY_RESERVED1 0x0300
115 #define IPV6_PRIORITY_BULK 0x0400
116 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
Datm.h43 #define ATM_NO_AAL 0 /* AAL not specified */
55 * SOL_SOCKET is 0xFFFF, so that's a bit of a problem
58 #define __SO_ENCODE(l,n,t) ((((l) & 0x1FF) << 22) | ((n) << 16) | \
60 #define __SO_LEVEL_MATCH(c,m) (((c) >> 22) == ((m) & 0x1FF))
61 #define __SO_NUMBER(c) (((c) >> 16) & 0x3f)
62 #define __SO_SIZE(c) ((c) & 0x3fff)
68 #define SO_SETCLP __SO_ENCODE(SOL_ATM,0,int)
94 #define ATM_HDR_GFC_MASK 0xf0000000
96 #define ATM_HDR_VPI_MASK 0x0ff00000
98 #define ATM_HDR_VCI_MASK 0x000ffff0
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx7d.dtsi17 cpu0: cpu@0 {
53 opp-supported-hw = <0xd>, <0x7>;
61 opp-supported-hw = <0xc>, <0x7>;
69 opp-supported-hw = <0x8>, <0x3>;
78 #phy-cells = <0>;
84 reg = <0x3007d000 0x1000>;
91 arm,primecell-periphid = <0xbb956>;
111 reg = <0x31001000 0x1000>,
112 <0x31002000 0x2000>,
113 <0x31004000 0x2000>,
[all …]
/linux-6.14.4/arch/arm/mach-versatile/
Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/b43legacy/
Dxmit.h46 #define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
48 #define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
50 #define B43legacy_TX4_MAC_LIFETIME 0x00001000
51 #define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
52 #define B43legacy_TX4_MAC_SENDCTS 0x00000400
53 #define B43legacy_TX4_MAC_AMPDU 0x00000300
55 #define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
56 #define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
57 #define B43legacy_TX4_MAC_5GHZ 0x00000080
58 #define B43legacy_TX4_MAC_IGNPMQ 0x00000020
[all …]
/linux-6.14.4/drivers/clk/
Dclk-highbank.c14 #define HB_PLL_LOCK_500 0x20000000
15 #define HB_PLL_LOCK 0x10000000
17 #define HB_PLL_DIVF_MASK 0x0ff00000
19 #define HB_PLL_DIVQ_MASK 0x00070000
21 #define HB_PLL_DIVR_MASK 0x00001f00
23 #define HB_PLL_RANGE_MASK 0x00000070
24 #define HB_PLL_BYPASS 0x00000008
25 #define HB_PLL_RESET 0x00000004
26 #define HB_PLL_EXT_BYPASS 0x00000002
27 #define HB_PLL_EXT_ENA 0x00000001
[all …]
/linux-6.14.4/arch/arm/boot/dts/qcom/
Dqcom-msm8926-htc-memul.dts50 reg = <0x05b00000 0x200000>;
55 reg = <0x07500000 0xb00000>;
60 reg = <0x08000000 0x4f00000>;
65 reg = <0x0cf00000 0x200000>;
70 reg = <0x0d100000 0x3a000>;
75 reg = <0x0d13a000 0xc6000>;
80 reg = <0x0d200000 0x650000>;
85 reg = <0x0d850000 0x3b0000>;
90 reg = <0x0dc00000 0x1400000>;
95 reg = <0x0f000000 0x500000>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/davinci/
Dda850-lcdk.dts24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x00 0x00101010 0x00f0f0f0
207 0x04 0x00000110 0x00000ff0
213 /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */
[all …]
Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath9k/
Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
/linux-6.14.4/arch/mips/include/asm/sgi/
Dheart.h24 #define HEART_XKPHYS_BASE ((void *)(IO_BASE | 0x000000000ff00000ULL))
47 * @__pad0: 0x0f40 bytes of padding -> next HEART register 0x01000.
49 * @__pad1: 0xeff8 bytes of padding -> next HEART register 0x10000.
56 * @__pad2: 0xffb8 bytes of padding -> next HEART register 0x20000.
58 * @__pad3: 0xfff8 bytes of padding -> next HEART register 0x30000.
60 * @__pad4: 0xfff8 bytes of padding -> next HEART register 0x40000.
62 * @__pad5: 0xfff8 bytes of padding -> next HEART register 0x50000.
64 * @__pad6: 0xfff8 bytes of padding -> next HEART register 0x60000.
79 struct ip30_heart_regs { /* 0x0ff00000 */
80 u64 mode; /* + 0x00000 */
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath5k/
Ddesc.h25 * @rx_control_0: RX control word 0
34 #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff /* data buffer length */
35 #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 /* RX interrupt request */
39 * @rx_status_0: RX status word 0
50 /* RX status word 0 fields/flags */
51 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff /* RX data length */
52 #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 /* more desc for this frame */
53 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210 0x00004000 /* [5210] receive on ant 1 */
54 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 /* reception rate */
56 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 /* rssi */
[all …]
/linux-6.14.4/drivers/net/wireless/ath/carl9170/
Dphy.h24 #define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
28 #define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
29 #define AR9170_PHY_TEST_AGC_CLR 0x10000000
30 #define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
32 #define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
33 #define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
34 #define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
35 #define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
36 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
37 #define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
[all …]
/linux-6.14.4/drivers/scsi/bfa/
Dbfi_reg.h18 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
19 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
20 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
21 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
22 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
23 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
24 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
25 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
27 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
28 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux-6.14.4/drivers/net/ethernet/brocade/bna/
Dbfi_reg.h19 #define HOSTFN0_INT_STATUS 0x00014000 /* cb/ct */
20 #define HOSTFN1_INT_STATUS 0x00014100 /* cb/ct */
21 #define HOSTFN2_INT_STATUS 0x00014300 /* ct */
22 #define HOSTFN3_INT_STATUS 0x00014400 /* ct */
23 #define HOSTFN0_INT_MSK 0x00014004 /* cb/ct */
24 #define HOSTFN1_INT_MSK 0x00014104 /* cb/ct */
25 #define HOSTFN2_INT_MSK 0x00014304 /* ct */
26 #define HOSTFN3_INT_MSK 0x00014404 /* ct */
28 #define HOST_PAGE_NUM_FN0 0x00014008 /* cb/ct */
29 #define HOST_PAGE_NUM_FN1 0x00014108 /* cb/ct */
[all …]
/linux-6.14.4/drivers/net/wireless/broadcom/b43/
Dxmit.h101 #define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */
102 #define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */
103 #define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */
104 #define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
105 #define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
107 #define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
108 #define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
110 #define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
111 #define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
112 #define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
[all …]

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