Lines Matching +full:0 +full:x0ff00000
14 #define HB_PLL_LOCK_500 0x20000000
15 #define HB_PLL_LOCK 0x10000000
17 #define HB_PLL_DIVF_MASK 0x0ff00000
19 #define HB_PLL_DIVQ_MASK 0x00070000
21 #define HB_PLL_DIVR_MASK 0x00001f00
23 #define HB_PLL_RANGE_MASK 0x00000070
24 #define HB_PLL_BYPASS 0x00000008
25 #define HB_PLL_RESET 0x00000004
26 #define HB_PLL_EXT_BYPASS 0x00000002
27 #define HB_PLL_EXT_ENA 0x00000001
33 #define HB_A9_BCLK_DIV_MASK 0x00000006
35 #define HB_A9_PCLK_DIV 0x00000001
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
57 return 0; in clk_pll_prepare()
79 return 0; in clk_pll_enable()
165 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_set_rate()
167 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_set_rate()
179 return 0; in clk_pll_set_rate()
223 div = readl(hbclk->reg) & 0x1f; in clk_periclk_recalc_rate()
237 div &= ~0x1; in clk_periclk_round_rate()
249 if (div & 0x1) in clk_periclk_set_rate()
253 return 0; in clk_periclk_set_rate()
282 hb_clk->reg = of_iomap(srnp, 0); in hb_clk_init()
292 parent_name = of_clk_get_parent_name(node, 0); in hb_clk_init()
308 hb_clk_init(node, &clk_pll_ops, 0); in hb_pll_init()
314 hb_clk_init(node, &a9periphclk_ops, 0); in hb_a9periph_init()
326 hb_clk_init(node, &periclk_ops, 0); in hb_emmc_init()