Lines Matching +full:0 +full:x0ff00000
101 #define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */
102 #define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */
103 #define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */
104 #define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
105 #define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
107 #define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
108 #define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
110 #define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
111 #define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
112 #define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
113 #define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
114 #define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
115 #define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
116 #define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
117 #define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
118 #define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
119 #define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
120 #define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
121 #define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
122 #define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
123 #define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
124 #define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
125 #define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
126 #define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
127 #define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
128 #define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
131 #define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
132 #define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
133 #define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
134 #define B43_TXH_EFT_FB_HT 0x02 /* HT */
135 #define B43_TXH_EFT_FB_VHT 0x03 /* VHT */
136 #define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
137 #define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
138 #define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
139 #define B43_TXH_EFT_RTS_HT 0x08 /* HT */
140 #define B43_TXH_EFT_RTS_VHT 0x0C /* VHT */
141 #define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
142 #define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
143 #define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
144 #define B43_TXH_EFT_RTSFB_HT 0x20 /* HT */
145 #define B43_TXH_EFT_RTSFB_VHT 0x30 /* VHT */
148 #define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
149 #define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
150 #define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
151 #define B43_TXH_PHY_ENC_HT 0x0002 /* HT */
152 #define B43_TXH_PHY_ENC_VHT 0x0003 /* VHT */
153 #define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
154 #define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
155 #define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
156 #define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
157 #define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
158 #define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
159 #define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
160 #define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
164 #define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
165 #define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
166 #define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
167 #define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
168 #define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
169 #define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
170 #define B43_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */
171 #define B43_TXH_PHY1_MODE 0x0038 /* Mode */
172 #define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
173 #define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
174 #define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
175 #define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
176 #define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
177 #define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
178 #define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
179 #define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
180 #define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
181 #define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
182 #define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
183 #define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
184 #define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
185 #define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
186 #define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
187 #define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
188 #define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
202 return 0; in b43_txhdr_size()
242 __le16 phy_status0; /* PHY RX Status 0 */
252 __s8 power0; /* PHY RX Status 1: Power 0 */
299 /* PHY RX Status 0 */
300 #define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
301 #define B43_RX_PHYST0_PLCPHCF 0x0200
302 #define B43_RX_PHYST0_PLCPFV 0x0100
303 #define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
304 #define B43_RX_PHYST0_LCRS 0x0040
305 #define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
306 #define B43_RX_PHYST0_UNSRATE 0x0010
307 #define B43_RX_PHYST0_CLIP 0x000C
309 #define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
310 #define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
311 #define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
312 #define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
313 #define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
316 #define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
318 #define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
320 #define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
323 #define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
325 #define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
328 #define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
329 #define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
330 #define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
331 #define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
333 #define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
334 #define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
335 #define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
337 #define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
338 #define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
339 #define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
340 #define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
341 #define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
344 #define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
345 #define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
346 #define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
348 #define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */