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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Dqcom,sc7180-dispcc.yaml57 reg = <0x0af00000 0x200000>;
60 <&dsi_phy 0>,
62 <&dp_phy 0>,
Dqcom,dispcc-sm6350.yaml57 reg = <0x0af00000 0x20000>;
60 <&dsi_phy 0>,
62 <&dp_phy 0>,
Dqcom,sm4450-dispcc.yaml60 reg = <0x0af00000 0x20000>;
Dqcom,sc7280-dispcc.yaml61 reg = <0x0af00000 0x200000>;
64 <&dsi_phy 0>,
66 <&dp_phy 0>,
68 <&edp_phy 0>,
Dqcom,sm7150-dispcc.yaml59 reg = <0x0af00000 0x200000>;
64 <&mdss_dsi0_phy 0>,
66 <&mdss_dsi1_phy 0>,
68 <&dp_phy 0>,
Dqcom,sdm845-dispcc.yaml66 reg = <0x0af00000 0x10000>;
70 <&dsi0_phy 0>,
72 <&dsi1_phy 0>,
74 <&dp_phy 0>,
Dqcom,sa8775p-dispcc.yaml61 reg = <0x0af00000 0x20000>;
66 <&dp_phy0 0>,
70 <&dsi_phy0 0>,
Dqcom,dispcc-sc8280xp.yaml30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
38 - description: DSI 0 PLL byte clock
39 - description: DSI 0 PLL DSI clock
64 reg = <0x0af00000 0x20000>;
68 <&mdss0_dp_phy0 0>,
70 <&mdss0_dp_phy1 0>,
72 <&mdss0_dp_phy2 0>,
74 <&mdss0_dp_phy3 0>,
76 <&mdss0_dsi0_phy 0>,
[all …]
Dqcom,sm8450-dispcc.yaml71 reg = <0x0af00000 0x10000>;
76 <&dsi0_phy 0>,
78 <&dsi1_phy 0>,
Dqcom,sm8550-dispcc.yaml78 reg = <0x0af00000 0x10000>;
83 <&dsi0_phy 0>,
85 <&dsi1_phy 0>,
87 <&dp0_phy 0>,
89 <&dp1_phy 0>,
91 <&dp2_phy 0>,
93 <&dp3_phy 0>,
Dqcom,dispcc-sm8x50.yaml102 reg = <0x0af00000 0x10000>;
104 <&dsi0_phy 0>,
106 <&dsi1_phy 0>,
108 <&dp_phy 0>,
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dsm4450.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
37 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
[all …]
Dsdm670.dtsi35 #clock-cells = <0>;
41 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0 0x0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
84 qcom,freq-domain = <&cpufreq_hw 0>;
102 reg = <0x0 0x200>;
106 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dqcs8300.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
42 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0x0 0x0>;
66 reg = <0x0 0x100>;
85 reg = <0x0 0x200>;
104 reg = <0x0 0x300>;
123 reg = <0x0 0x10000>;
142 reg = <0x0 0x10100>;
[all …]
Dsm6350.dtsi32 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0x0 0x0>;
52 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8180x.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x0>;
52 qcom,freq-domain = <&cpufreq_hw 0>;
59 clocks = <&cpufreq_hw 0>;
77 reg = <0x0 0x100>;
81 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8350.dtsi38 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
58 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
82 clocks = <&cpufreq_hw 0>;
85 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi66 #clock-cells = <0>;
72 #clock-cells = <0>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0x0 0x0>;
84 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domain = <&cpufreq_hw 0>;
112 reg = <0x0 0x100>;
113 clocks = <&cpufreq_hw 0>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi34 #clock-cells = <0>;
41 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
62 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
83 reg = <0x0 0x100>;
84 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8550.dtsi39 #clock-cells = <0>;
44 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
66 #size-cells = <0>;
68 cpu0: cpu@0 {
71 reg = <0 0>;
72 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domain = <&cpufreq_hw 0>;
97 reg = <0 0x100>;
[all …]
Dsm8450.dtsi39 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0 0x0>;
62 qcom,freq-domain = <&cpufreq_hw 0>;
64 clocks = <&cpufreq_hw 0>;
81 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
88 clocks = <&cpufreq_hw 0>;
[all …]
Dsm8650.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
59 #clock-cells = <0>;
69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0 0>;
76 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0 0x100>;
[all …]
Dsdm845.dtsi78 #clock-cells = <0>;
85 #clock-cells = <0>;
92 #size-cells = <0>;
94 cpu0: cpu@0 {
97 reg = <0x0 0x0>;
98 clocks = <&cpufreq_hw 0>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
126 reg = <0x0 0x100>;
127 clocks = <&cpufreq_hw 0>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi33 #clock-cells = <0>;
38 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsa8775p.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
89 reg = <0x0 0x200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]

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