Searched +full:0 +full:x0ae95500 (Results 1 – 4 of 4) sorted by relevance
38 "^display-controller@[0-9a-f]+$":45 "^displayport-controller@[0-9a-f]+$":52 "^dsi@[0-9a-f]+$":61 "^phy@[0-9a-f]+$":81 reg = <0x0ae00000 0x1000>;97 iommus = <&apps_smmu 0x1c00 0x2>;105 reg = <0x0ae01000 0x8f000>,106 <0x0aeb0000 0x2008>;127 interrupts = <0>;131 #size-cells = <0>;[all …]
39 "^display-controller@[0-9a-f]+$":47 "^displayport-controller@[0-9a-f]+$":57 "^dsi@[0-9a-f]+$":67 "^phy@[0-9a-f]+$":91 reg = <0x0ae00000 0x1000>;94 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,95 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;112 iommus = <&apps_smmu 0x1c00 0x2>;120 reg = <0x0ae01000 0x8f000>,121 <0x0aeb0000 0x2008>;[all …]
39 #clock-cells = <0>;44 #clock-cells = <0>;48 #clock-cells = <0>;56 #clock-cells = <0>;66 #size-cells = <0>;68 cpu0: cpu@0 {71 reg = <0 0>;72 clocks = <&cpufreq_hw 0>;77 qcom,freq-domain = <&cpufreq_hw 0>;97 reg = <0 0x100>;[all …]
40 #clock-cells = <0>;45 #clock-cells = <0>;50 #clock-cells = <0>;59 #clock-cells = <0>;69 #size-cells = <0>;71 cpu0: cpu@0 {74 reg = <0 0>;76 clocks = <&cpufreq_hw 0>;86 qcom,freq-domain = <&cpufreq_hw 0>;107 reg = <0 0x100>;[all …]