Searched +full:0 +full:x01e20000 (Results 1 – 11 of 11) sorted by relevance
27 #define DA8XX_TPCC_BASE 0x01c0000028 #define DA8XX_TPTC0_BASE 0x01c0800029 #define DA8XX_TPTC1_BASE 0x01c0840030 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */31 #define DA8XX_I2C0_BASE 0x01c2200032 #define DA8XX_RTC_BASE 0x01c2300033 #define DA8XX_PRUSS_MEM_BASE 0x01c3000034 #define DA8XX_MMCSD0_BASE 0x01c4000035 #define DA8XX_SPI0_BASE 0x01c4100036 #define DA830_SPI1_BASE 0x01e12000[all …]
66 "^iommu-ctx@[0-9a-f]+$":111 reg = <0x01ef0000 0x3000>;119 ranges = <0 0x01e20000 0x40000>;124 reg = <0x4000 0x1000>;
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
26 #clock-cells = <0>;32 #size-cells = <0>;34 cpu0: cpu@0 {37 reg = <0x0>;48 reg = <0x1>;59 reg = <0x2>;70 reg = <0x3>;81 reg = <0x100>;92 reg = <0x101>;103 reg = <0x102>;[all …]
20 #clock-cells = <0>;25 #clock-cells = <0>;31 #size-cells = <0>;35 reg = <0x100>;54 reg = <0x101>;67 reg = <0x102>;80 reg = <0x103>;112 cluster_sleep_0: cluster-sleep-0 {114 arm,psci-suspend-param = <0x41000053>;124 cpu_sleep_0: cpu-sleep-0 {[all …]
25 #clock-cells = <0>;31 #clock-cells = <0>;39 #size-cells = <0>;41 cpu0: cpu@0 {44 reg = <0x0>;54 reg = <0x1>;64 reg = <0x2>;74 reg = <0x3>;84 reg = <0x100>;94 reg = <0x101>;[all …]
30 #clock-cells = <0>;36 #clock-cells = <0>;43 #size-cells = <0>;49 reg = <0x100>;67 reg = <0x101>;80 reg = <0x102>;93 reg = <0x103>;102 cpu4: cpu@0 {106 reg = <0x0>;124 reg = <0x1>;[all …]
27 reg = <0 0x80000000 0 0>;36 reg = <0x0 0x86000000 0x0 0x300000>;42 reg = <0x0 0x86300000 0x0 0x100000>;50 reg = <0x0 0x86400000 0x0 0x100000>;55 reg = <0x0 0x86500000 0x0 0x180000>;60 reg = <0x0 0x86680000 0x0 0x80000>;66 reg = <0x0 0x86700000 0x0 0xe0000>;73 reg = <0x0 0x867e0000 0x0 0x20000>;85 * alignment = <0x0 0x400000>;86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;[all …]
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major62 module_param(debug_level, int, 0);90 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */91 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */92 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */93 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */94 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */95 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */96 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */97 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */[all …]