1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies legacy IOMMU implementations
8
9maintainers:
10  - Konrad Dybcio <[email protected]>
11
12description: |
13  Qualcomm "B" family devices which are not compatible with arm-smmu have
14  a similar looking IOMMU, but without access to the global register space
15  and optionally requiring additional configuration to route context IRQs
16  to non-secure vs secure interrupt line.
17
18properties:
19  compatible:
20    oneOf:
21      - items:
22          - enum:
23              - qcom,msm8916-iommu
24              - qcom,msm8917-iommu
25              - qcom,msm8953-iommu
26          - const: qcom,msm-iommu-v1
27      - items:
28          - enum:
29              - qcom,msm8953-iommu
30              - qcom,msm8976-iommu
31          - const: qcom,msm-iommu-v2
32
33  clocks:
34    items:
35      - description: Clock required for IOMMU register group access
36      - description: Clock required for underlying bus access
37
38  clock-names:
39    items:
40      - const: iface
41      - const: bus
42
43  power-domains:
44    maxItems: 1
45
46  reg:
47    maxItems: 1
48
49  ranges: true
50
51  qcom,iommu-secure-id:
52    $ref: /schemas/types.yaml#/definitions/uint32
53    description:
54      The SCM secure ID of the IOMMU instance.
55
56  '#address-cells':
57    const: 1
58
59  '#size-cells':
60    const: 1
61
62  '#iommu-cells':
63    const: 1
64
65patternProperties:
66  "^iommu-ctx@[0-9a-f]+$":
67    type: object
68    additionalProperties: false
69    properties:
70      compatible:
71        enum:
72          - qcom,msm-iommu-v1-ns
73          - qcom,msm-iommu-v1-sec
74          - qcom,msm-iommu-v2-ns
75          - qcom,msm-iommu-v2-sec
76
77      interrupts:
78        maxItems: 1
79
80      reg:
81        maxItems: 1
82
83      qcom,ctx-asid:
84        $ref: /schemas/types.yaml#/definitions/uint32
85        description:
86          The ASID number associated to the context bank.
87
88    required:
89      - compatible
90      - interrupts
91      - reg
92
93required:
94  - compatible
95  - clocks
96  - clock-names
97  - ranges
98  - '#address-cells'
99  - '#size-cells'
100  - '#iommu-cells'
101
102additionalProperties: false
103
104examples:
105  - |
106    #include <dt-bindings/clock/qcom,gcc-msm8916.h>
107    #include <dt-bindings/interrupt-controller/arm-gic.h>
108
109    apps_iommu: iommu@1e20000 {
110      compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
111      reg = <0x01ef0000 0x3000>;
112      clocks = <&gcc GCC_SMMU_CFG_CLK>,
113               <&gcc GCC_APSS_TCU_CLK>;
114      clock-names = "iface", "bus";
115      qcom,iommu-secure-id = <17>;
116      #address-cells = <1>;
117      #size-cells = <1>;
118      #iommu-cells = <1>;
119      ranges = <0 0x01e20000 0x40000>;
120
121      /* mdp_0: */
122      iommu-ctx@4000 {
123        compatible = "qcom,msm-iommu-v1-ns";
124        reg = <0x4000 0x1000>;
125        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
126      };
127    };
128