11  * 0-5 A number of folks worked on this driver in bits and pieces but the major
62 module_param(debug_level, int, 0);
90 #define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC up to frames */
91 #define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
92 #define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
93 #define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
94 #define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
95 #define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
96 #define EMAC_DEF_PROM_EN		(0) /* Promiscuous disabled */
97 #define EMAC_DEF_PROM_CH		(0) /* Promiscuous channel is 0 */
99 #define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
101 #define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */
104 #define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/
106 #define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
109 #define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
110 #define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
120 #define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
122 #define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
123 #define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
124 #define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
125 #define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
126 #define EMAC_INT_MASK_CLEAR		(0xFF)
137 #define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
140 #define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
142 #define EMAC_RXMBP_MULTICH_SHIFT	(0)
143 #define EMAC_RXMBP_MULTICH_MASK		(0x7)
144 #define EMAC_RXMBP_CHMASK		(0x7)
147 # define EMAC_MBP_RXPROMISC		(0x00200000)
148 # define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
149 # define EMAC_MBP_RXBCAST		(0x00002000)
150 # define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
151 # define EMAC_MBP_RXMCAST		(0x00000020)
152 # define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)
159 #define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
167 #define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
169 #define EMAC_MACSTATUS_TXERRCH_MASK	(0x70000)
171 #define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
173 #define EMAC_MACSTATUS_RXERRCH_MASK	(0x700)
177 #define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
178 #define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)
180 /* MAC_IN_VECTOR (0x180) register bit fields */
184 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
199 #define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
201 #define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)
208 #define EMAC_MACINVECTOR	0x90
210 #define EMAC_DM646X_MACEOIVECTOR	0x94
212 #define EMAC_MACINTSTATRAW	0xB0
213 #define EMAC_MACINTSTATMASKED	0xB4
214 #define EMAC_MACINTMASKSET	0xB8
215 #define EMAC_MACINTMASKCLEAR	0xBC
217 #define EMAC_RXMBPENABLE	0x100
218 #define EMAC_RXUNICASTSET	0x104
219 #define EMAC_RXUNICASTCLEAR	0x108
220 #define EMAC_RXMAXLEN		0x10C
221 #define EMAC_RXBUFFEROFFSET	0x110
222 #define EMAC_RXFILTERLOWTHRESH	0x114
224 #define EMAC_MACCONTROL		0x160
225 #define EMAC_MACSTATUS		0x164
226 #define EMAC_EMCONTROL		0x168
227 #define EMAC_FIFOCONTROL	0x16C
228 #define EMAC_MACCONFIG		0x170
229 #define EMAC_SOFTRESET		0x174
230 #define EMAC_MACSRCADDRLO	0x1D0
231 #define EMAC_MACSRCADDRHI	0x1D4
232 #define EMAC_MACHASH1		0x1D8
233 #define EMAC_MACHASH2		0x1DC
234 #define EMAC_MACADDRLO		0x500
235 #define EMAC_MACADDRHI		0x504
236 #define EMAC_MACINDEX		0x508
239 #define EMAC_RXGOODFRAMES	0x200
240 #define EMAC_RXBCASTFRAMES	0x204
241 #define EMAC_RXMCASTFRAMES	0x208
242 #define EMAC_RXPAUSEFRAMES	0x20C
243 #define EMAC_RXCRCERRORS	0x210
244 #define EMAC_RXALIGNCODEERRORS	0x214
245 #define EMAC_RXOVERSIZED	0x218
246 #define EMAC_RXJABBER		0x21C
247 #define EMAC_RXUNDERSIZED	0x220
248 #define EMAC_RXFRAGMENTS	0x224
249 #define EMAC_RXFILTERED		0x228
250 #define EMAC_RXQOSFILTERED	0x22C
251 #define EMAC_RXOCTETS		0x230
252 #define EMAC_TXGOODFRAMES	0x234
253 #define EMAC_TXBCASTFRAMES	0x238
254 #define EMAC_TXMCASTFRAMES	0x23C
255 #define EMAC_TXPAUSEFRAMES	0x240
256 #define EMAC_TXDEFERRED		0x244
257 #define EMAC_TXCOLLISION	0x248
258 #define EMAC_TXSINGLECOLL	0x24C
259 #define EMAC_TXMULTICOLL	0x250
260 #define EMAC_TXEXCESSIVECOLL	0x254
261 #define EMAC_TXLATECOLL		0x258
262 #define EMAC_TXUNDERRUN		0x25C
263 #define EMAC_TXCARRIERSENSE	0x260
264 #define EMAC_TXOCTETS		0x264
265 #define EMAC_NETOCTETS		0x280
266 #define EMAC_RXSOFOVERRUNS	0x284
267 #define EMAC_RXMOFOVERRUNS	0x288
268 #define EMAC_RXDMAOVERRUNS	0x28C
271 #define EMAC_CTRL_EWCTL		(0x4)
272 #define EMAC_CTRL_EWINTTCNT	(0x8)
275 #define EMAC_DM644X_EWINTCNT_MASK	0x1FFFF
276 #define EMAC_DM644X_INTMIN_INTVL	0x1
280 #define EMAC_DM646X_CMINTCTRL	0x0C
281 #define EMAC_DM646X_CMRXINTEN	0x14
282 #define EMAC_DM646X_CMTXINTEN	0x18
283 #define EMAC_DM646X_CMRXINTMAX	0x70
284 #define EMAC_DM646X_CMTXINTMAX	0x74
287 #define EMAC_DM646X_INTPACEEN		(0x3 << 16)
288 #define EMAC_DM646X_INTPRESCALE_MASK	(0x7FF << 0)
296 #define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
297 #define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)
300 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
319 	u32 link; /* 1=link on, 0=link off */
320 	u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
321 	u32 duplex; /* Link duplex: 0=Half, 1=Full */
397 	return 0;  in emac_get_coalesce()
417 	u32 int_ctrl, num_interrupts = 0;  in emac_set_coalesce()
418 	u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;  in emac_set_coalesce()
421 		priv->coal_intvl = 0;  in emac_set_coalesce()
425 			emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0);  in emac_set_coalesce()
428 			emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0);  in emac_set_coalesce()
432 		return 0;  in emac_set_coalesce()
491 	return 0;  in emac_set_coalesce()
589 	hash = 0;  in hash_get()
591 	for (cnt = 0; cnt < 2; cnt++) {  in hash_get()
600 	return hash & 0x3F;  in hash_get()
614 	u32 rc = 0;  in emac_hash_add()
628 	if (priv->multicast_hash_cnt[hash_value] == 0) {  in emac_hash_add()
659 	if (priv->multicast_hash_cnt[hash_value] > 0) {  in emac_hash_del()
664 	/* if counter still > 0, at least one multicast address refers  in emac_hash_del()
665 	 * to this hash bit. so return 0 */  in emac_hash_del()
666 	if (priv->multicast_hash_cnt[hash_value] > 0)  in emac_hash_del()
667 		return 0;  in emac_hash_del()
682 #define EMAC_MULTICAST_ADD	0
715 		priv->mac_hash1 = 0;  in emac_add_mcast()
716 		priv->mac_hash2 = 0;  in emac_add_mcast()
717 		memset(&(priv->multicast_hash_cnt[0]), 0,  in emac_add_mcast()
718 		sizeof(priv->multicast_hash_cnt[0]) *  in emac_add_mcast()
729 	if (update > 0) {  in emac_add_mcast()
796 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);  in emac_int_disable()
797 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);  in emac_int_disable()
816 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);  in emac_int_disable()
833 		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);  in emac_int_enable()
834 		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);  in emac_int_enable()
843 		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);  in emac_int_enable()
896 	if (status < 0) {  in emac_rx_handler()
918 			skb_tailroom(skb), 0);  in emac_rx_handler()
921 	if (unlikely(ret < 0))  in emac_rx_handler()
964 	if (unlikely(ret_code < 0)) {  in emac_dev_xmit()
973 				     0);  in emac_dev_xmit()
974 	if (unlikely(ret_code != 0)) {  in emac_dev_xmit()
1028  * Returns success (0) or appropriate error code (none as of now)
1037 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type0addr()
1055  * Returns success (0) or appropriate error code (none as of now)
1064 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type1addr()
1079  * Returns success (0) or appropriate error code (none as of now)
1087 	       (mac_addr[1] << 8) | (mac_addr[0]));  in emac_set_type2addr()
1089 	val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \  in emac_set_type2addr()
1103  * Returns success (0) or appropriate error code (none as of now)
1109 	if (priv->rx_addr_type == 0) {  in emac_setmac()
1113 		for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)  in emac_setmac()
1131  * Returns success (0) or appropriate error code (none as of now)
1155 	return 0;  in emac_dev_setmac_addr()
1165  * Returns success (0) or appropriate error code (none right now)
1181 		(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |  in emac_hw_enable()
1182 		((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |  in emac_hw_enable()
1183 		((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |  in emac_hw_enable()
1184 		((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));  in emac_hw_enable()
1188 		(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |  in emac_hw_enable()
1189 		((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |  in emac_hw_enable()
1190 		 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |  in emac_hw_enable()
1191 		 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |  in emac_hw_enable()
1192 		 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |  in emac_hw_enable()
1193 		 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |  in emac_hw_enable()
1194 		 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |  in emac_hw_enable()
1197 		 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |  in emac_hw_enable()
1200 		 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |  in emac_hw_enable()
1208 	emac_write(EMAC_RXFILTERLOWTHRESH, 0);  in emac_hw_enable()
1210 	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;  in emac_hw_enable()
1224 	return 0;  in emac_hw_enable()
1247 	u32 status = 0;  in emac_poll()
1248 	u32 num_rx_pkts = 0;  in emac_poll()
1289 					&emac_txhost_errcodes[cause][0], ch);  in emac_poll()
1299 					&emac_rxhost_errcodes[cause][0], ch);  in emac_poll()
1332 	int new_state = 0;  in emac_adjust_link()
1353 		priv->link = 0;  in emac_adjust_link()
1354 		priv->speed = 0;  in emac_adjust_link()
1355 		priv->duplex = ~0;  in emac_adjust_link()
1377  * Returns success(0) or appropriate error code
1409  * Returns 0 for a successful open, or appropriate error code
1416 	int res_num = 0, irq_num = 0;  in emac_dev_open()
1417 	int i = 0;  in emac_dev_open()
1423 	if (ret < 0) {  in emac_dev_open()
1435 	priv->mac_hash1 = 0;  in emac_dev_open()
1436 	priv->mac_hash2 = 0;  in emac_dev_open()
1437 	emac_write(EMAC_MACHASH1, 0);  in emac_dev_open()
1438 	emac_write(EMAC_MACHASH2, 0);  in emac_dev_open()
1440 	for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {  in emac_dev_open()
1447 					     skb_tailroom(skb), 0);  in emac_dev_open()
1448 		if (WARN_ON(ret < 0))  in emac_dev_open()
1455 			if (ret < 0)  in emac_dev_open()
1458 			ret = request_irq(ret, emac_irq, 0, ndev->name, ndev);  in emac_dev_open()
1468 				ret = request_irq(irq_num, emac_irq, 0, ndev->name, ndev);  in emac_dev_open()
1485 	if (priv->coal_intvl != 0) {  in emac_dev_open()
1496 					&emac_adjust_link, 0, 0);  in emac_dev_open()
1509 		 * some systems it can be 'davinci_mdio.0' so we need to use  in emac_dev_open()
1534 		priv->link = 0;  in emac_dev_open()
1535 		priv->speed = 0;  in emac_dev_open()
1536 		priv->duplex = ~0;  in emac_dev_open()
1556 	return 0;  in emac_dev_open()
1564 		for (q = res_num - 1; q >= 0; q--) {  in emac_dev_open()
1566 			if (irq_num > 0)  in emac_dev_open()
1570 		for (q = res_num; q >= 0; q--) {  in emac_dev_open()
1599 	int i = 0;  in emac_dev_stop()
1603 	int ret = 0;  in emac_dev_stop()
1621 			if (ret < 0 && ret != -ENXIO)  in emac_dev_stop()
1623 			if (ret > 0) {  in emac_dev_stop()
1626 				ret = 0;  in emac_dev_stop()
1661 	if (err < 0) {  in emac_dev_getnetstats()
1674 		stats_clear_mask = 0;  in emac_dev_getnetstats()
1763 	priv->phy_node = of_parse_phandle(np, "phy-handle", 0);  in davinci_emac_of_get_pdata()
1767 		else if (of_phy_register_fixed_link(np) >= 0)  in davinci_emac_of_get_pdata()
1806 	int rc = 0;  in davinci_emac_probe()
1855 	priv->coal_intvl = 0;  in davinci_emac_probe()
1859 	priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in davinci_emac_probe()
1885 	memset(&dma_params, 0, sizeof(dma_params));  in davinci_emac_probe()
1888 	dma_params.rxthresh		= priv->emac_base + 0x120;  in davinci_emac_probe()
1889 	dma_params.rxfree		= priv->emac_base + 0x140;  in davinci_emac_probe()
1890 	dma_params.txhdp		= priv->emac_base + 0x600;  in davinci_emac_probe()
1891 	dma_params.rxhdp		= priv->emac_base + 0x620;  in davinci_emac_probe()
1892 	dma_params.txcp			= priv->emac_base + 0x640;  in davinci_emac_probe()
1893 	dma_params.rxcp			= priv->emac_base + 0x660;  in davinci_emac_probe()
1900 	dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :  in davinci_emac_probe()
1911 					 emac_tx_handler, 0);  in davinci_emac_probe()
1926 	rc = platform_get_irq(pdev, 0);  in davinci_emac_probe()
1927 	if (rc < 0)  in davinci_emac_probe()
1933 		rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);  in davinci_emac_probe()
1951 	if (rc < 0) {  in davinci_emac_probe()
1975 	return 0;  in davinci_emac_probe()
2030 	return 0;  in davinci_emac_suspend()
2040 	return 0;  in davinci_emac_resume()
2050 	.hw_ram_addr		= 0x01e20000,