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/linux-6.14.4/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <[email protected]>
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14 and MSSR (Module Standby and Software Reset) blocks are intimately connected,
18 - The CPG block generates various core clocks,
19 - The MSSR block provides two functions:
27 - renesas,r7s9210-cpg-mssr # RZ/A2
[all …]
/linux-6.14.4/drivers/clk/renesas/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
4 obj-$(CONFIG_CLK_RZA1) += clk-rz.o
5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
6 obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
7 obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
[all …]
Drenesas-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on clk-mstp.c, clk-rcar-gen2.c, and clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
28 #include <linux/reset-controller.h>
31 #include <dt-bindings/clock/renesas-cpg-mssr.h>
33 #include "renesas-cpg-mssr.h"
34 #include "clk-div6.h"
45 * If the registers exist, these are valid for SH-Mobile, R-Mobile,
46 * R-Car Gen2, R-Car Gen3, and RZ/G1.
47 * These are NOT valid for R-Car Gen1 and RZ/A1!
[all …]
Dr7s9210-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on r8a7795-cpg-mssr.c
13 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
16 #include "renesas-cpg-mssr.h"
169 parent = clks[core->parent]; in rza2_cpg_clk_register()
173 switch (core->id) { in rza2_cpg_clk_register()
185 return ERR_PTR(-EINVAL); in rza2_cpg_clk_register()
188 if (core->id == CLK_MAIN) in rza2_cpg_clk_register()
191 return clk_register_fixed_factor(NULL, core->name, in rza2_cpg_clk_register()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
62 bool "R-Mobile APE6 clock support" if COMPILE_TEST
67 bool "R-Mobile A1 clock support" if COMPILE_TEST
104 bool "R-Car M1A clock support" if COMPILE_TEST
108 bool "R-Car H1 clock support" if COMPILE_TEST
112 bool "R-Car H2 clock support" if COMPILE_TEST
116 bool "R-Car M2-W/N clock support" if COMPILE_TEST
120 bool "R-Car V2H clock support" if COMPILE_TEST
124 bool "R-Car E2 clock support" if COMPILE_TEST
128 bool "R-Car H3 clock support" if COMPILE_TEST
[all …]
Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-cpg-lib.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
[all …]
Dr8a779f0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a779a0-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen4-cpg.h"
152 DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
153 DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
167 DEF_MOD("ether-serdes", 1506, R8A779F0_CLK_S0D2_HSC),
[all …]
Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
139 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
[all …]
Drenesas-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Definitions of CPG Core Clocks
15 * - Clock outputs exported to DT
16 * - External input clocks
17 * - Internal CPG clocks
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95 * SoC-specific CPG/MSSR Description
114 * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
[all …]
Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
129 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
130 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
139 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
140 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
[all …]
/linux-6.14.4/arch/arm/mach-shmobile/
Dsetup-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 support
12 #include <linux/dma-map-ops.h>
23 #include "rcar-gen2.h"
26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/media/
Drenesas,vsp1.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <[email protected]>
13 The VSP is a video processing engine that supports up-/down-scaling, alpha
15 It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
20 - enum:
21 - renesas,r9a07g044-vsp2 # RZ/G2L
22 - renesas,vsp1 # R-Car Gen2 and RZ/G1
23 - renesas,vsp2 # R-Car Gen3 and RZ/G2
[all …]
Drenesas,vin.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <[email protected]>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
25 - items:
26 - enum:
[all …]
Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <[email protected]>
11 - Fabrizio Castro <[email protected]>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/thermal/
Drcar-gen3-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
5 $id: http://devicetree.org/schemas/thermal/rcar-gen3-thermal.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Gen3 Thermal Sensor
11 On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC)
16 - Niklas Söderlund <[email protected]>
18 $ref: thermal-sensor.yaml#
23 - renesas,r8a774a1-thermal # RZ/G2M
24 - renesas,r8a774b1-thermal # RZ/G2N
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/bridge/
Drenesas,lvds.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car LVDS Encoder
10 - Laurent Pinchart <[email protected]>
13 These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14 Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dr7s9210-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
12 /* R7S9210 CPG Core Clocks */
Dr8a7795-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a7795 CPG Core Clocks */
59 /* r8a7795 ES2.0 CPG Core Clocks */
Dr8a77470-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a77470 CPG Core Clocks */
Dr8a7792-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
9 #include <dt-bindings/clock/renesas-cpg-mssr.h>
11 /* r8a7792 CPG Core Clocks */
Dr8a7742-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a7742 CPG Core Clocks */
Dr8a7745-cpg-mssr.h1 /* SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
10 /* r8a7745 CPG Core Clocks */
/linux-6.14.4/Documentation/devicetree/bindings/phy/
Drenesas,rcar-gen3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Generation 3 PCIe PHY
10 - Sergei Shtylyov <[email protected]>
14 const: renesas,r8a77980-pcie-phy
22 power-domains:
28 '#phy-cells':
32 - compatible
[all …]
Drenesas,r8a779f0-ether-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yoshihiro Shimoda <[email protected]>
14 const: renesas,r8a779f0-ether-serdes
25 power-domains:
28 '#phy-cells':
33 - compatible
34 - reg
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/ufs/
Drenesas,ufs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car UFS Host Controller
10 - Yoshihiro Shimoda <[email protected]>
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
25 clock-names:
27 - const: fck
28 - const: ref_clk
[all …]

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