Lines Matching +full:- +full:cpg +full:- +full:mssr

1 /* SPDX-License-Identifier: GPL-2.0 */
12      * Definitions of CPG Core Clocks
15      *   - Clock outputs exported to DT
16      *   - External input clocks
17      *   - Internal CPG clocks
70 /* Convert from sparse base-100 to packed index space */
71 #define MOD_CLK_PACK(x)	((x) - ((x) / 100) * (100 - 32))
78 /* Convert from sparse base-10 to packed index space */
95      * SoC-specific CPG/MSSR Description
114      * @reg_layout: CPG/MSSR register layout from enum clk_reg_layout
120      * @init: Optional callback to perform SoC-specific initialization