Lines Matching +full:- +full:cpg +full:- +full:mssr
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-cpg-lib.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
126 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
132 DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
134 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
135 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
158 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
159 DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
169 MOD_CLK_ID(408), /* INTC-AP (GIC) */
173 * CPG Clock Data
179 *-------------------------------------------------
229 switch (core->type) { in r8a77970_cpg_clk_register()
243 parent = clks[core->parent]; in r8a77970_cpg_clk_register()
247 return clk_register_divider_table(NULL, core->name, in r8a77970_cpg_clk_register()