| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1662 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1664 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1666 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
1668 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::psub0)) in printVectorList() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1282 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1284 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1286 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3337 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3354 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3408 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3473 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4314 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5174 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5221 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3356 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3373 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3427 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3492 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4333 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5275 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5322 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
|
| /aosp_15_r20/external/llvm/lib/Target/AArch64/InstPrinter/ |
| H A D | AArch64InstPrinter.cpp | 1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 375 unsigned FirstReg = 0; in CreateRegs() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 382 Register FirstReg; in CreateRegs() local
|
| /aosp_15_r20/external/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
|
| /aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 382 unsigned FirstReg = 0; in CreateRegs() local
|
| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2057 unsigned &FirstReg, in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2149 unsigned &FirstReg, in CanFormLdStDWord()
2316 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 494 unsigned FirstReg = 0; in ScanInstruction() local
|
| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0; in ScanInstruction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 505 unsigned FirstReg = 0; in ScanInstruction() local
|
| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4307 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4360 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4507 unsigned FirstReg = 0; in HandleByVal() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 2258 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord()
2420 Register FirstReg, SecondReg; in RescheduleOps() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1787 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
4385 unsigned FirstReg, ElementWidth; in tryParseMatrixTileList() local
4481 MCRegister FirstReg; in tryParseVectorList() local
7713 MCRegister FirstReg; in tryParseGPRSeqPair() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4348 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4401 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4548 unsigned FirstReg = 0; in HandleByVal() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3343 unsigned FirstReg; in tryParseVectorList() local
5604 unsigned FirstReg; in tryParseGPRSeqPair() local
|
| /aosp_15_r20/external/capstone/arch/AArch64/ |
| H A D | AArch64InstPrinter.c | 1352 unsigned NumRegs = 1, FirstReg, i; in printVectorList() local
|
| /aosp_15_r20/external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /aosp_15_r20/external/swiftshader/third_party/subzero/src/ |
| H A D | IceTargetLoweringMIPS32.cpp | 1895 const auto FirstReg = in legalizeMov() local
1967 const auto FirstReg = in legalizeMov() local
2054 const auto FirstReg = in legalizeMov() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2550 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
|