| #
666fc6d1 |
| 23-Feb-2019 |
Zihao Yu <[email protected]> |
test,top,SimMMIO: fix timer address to match fpga implmentation
|
| #
9753d040 |
| 21-Feb-2019 |
Zihao Yu <[email protected]> |
test,top,SimMMIO: add uartlite stat and ctrl registers and map them to zero reg
|
| #
16287861 |
| 19-Feb-2019 |
Zihao Yu <[email protected]> |
memory: add AHBRAM and pass microbench
|
| #
397eaf0e |
| 16-Feb-2019 |
Zihao Yu <[email protected]> |
noop,IFU: support blocking instruction fetch
|
| #
52fcd981 |
| 16-Feb-2019 |
Zihao Yu <[email protected]> |
memory: add memory package
|
| #
7a4f04e7 |
| 16-Feb-2019 |
Zihao Yu <[email protected]> |
refactor memory
|