1package top 2 3import chisel3._ 4import chisel3.util._ 5 6import memory.MemIO 7 8class SimMMIO extends Module { 9 val io = IO(new Bundle { 10 val rw = Flipped(new MemIO) 11 val mmioTrap = new Bundle { 12 val valid = Output(Bool()) 13 val cmd = Output(UInt(3.W)) 14 val rdata = Input(UInt(32.W)) 15 } 16 }) 17 18 val wen = io.rw.a.valid && io.rw.w.valid 19 val wdataVec = VecInit.tabulate(4) { i => io.rw.w.bits.data(8 * (i + 1) - 1, 8 * i) } 20 val wmask = VecInit.tabulate(4) { i => io.rw.w.bits.mask(i).toBool } 21 22 io.mmioTrap.valid := false.B 23 io.mmioTrap.cmd := 0.U 24 25 when (io.rw.a.valid) { 26 switch (io.rw.a.bits.addr) { 27 is (0x43f8.U) { 28 when (wen) { printf("%c", wdataVec(0)) } 29 } 30 is (0x4048.U) { 31 // read RTC 32 io.mmioTrap.valid := true.B 33 io.mmioTrap.cmd := 0.U 34 } 35 is (0x4060.U) { 36 // read key 37 io.mmioTrap.valid := true.B 38 io.mmioTrap.cmd := 1.U 39 } 40 is (0x4100.U) { 41 // read screen size 42 io.mmioTrap.valid := true.B 43 io.mmioTrap.cmd := 2.U 44 } 45 is (0x4104.U) { 46 // write vga sync 47 io.mmioTrap.valid := true.B 48 io.mmioTrap.cmd := 4.U 49 } 50 } 51 52 when (io.rw.a.bits.addr >= 0x40000.U && io.rw.a.bits.addr < 0xc0000.U && wen) { 53 // write to vmem 54 io.mmioTrap.valid := true.B 55 io.mmioTrap.cmd := 5.U 56 } 57 } 58 59 io.rw.a.ready := true.B 60 io.rw.r.bits.data := io.mmioTrap.rdata 61 io.rw.r.valid := io.mmioTrap.valid 62} 63