bpu: remove stage 3

bpu: timing optimizations

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

Merge remote-tracking branch 'origin/master' into bpu-timing

Merge pull request #1247 from OpenXiangShan/ftq-timing

ftq: optimize ifu request timing

bpu: timing optimizations

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMux

bpu: timing optimizations

* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator

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ftq: let the 'range' of nextRangeAddr be 64 Bytes

ftq: code clean ups

ftq: optimize ifu request timing

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

bpu: use circular buffer as global history register, and

* use compressed info to do redirects
* implement folded history class

IFU: mmio instruction fetch waits for commit and flush frontend (#1196)

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruct

IFU: mmio instruction fetch waits for commit and flush frontend (#1196)

* IFU: move mmio to f3 and wait commit

* IFU: fix mmio_has_commit condition

* compare FtqPtr to ensure the mmio instruction has been committed

* Uncache fetch : cancel flush when backend redirect

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Merge branch 'master' into ftb-tail-shared

add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

Merge branch 'master' into decoupled-frontend

ftq: fix bugs when shareTailSlot is false

rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* is

rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

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Merge pull request #1039 from OpenXiangShan/ftb-lru

Modify FTB replacement strategy to PLRU

BPU: Fix bug that update read override predict read result

BPU: Fix FTB Replacement bug

ftq: add performance counters for mispredicts and corrects from each

bp stage of each cfi type

frontend: let br/jmp share the last slot of an ftb entry, ghist update timing optimization

core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

BPU: Modify FTB to update each 2 cycles

frontend: fix parameterization issue

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters