bpu,ftq: remove oversize logic

Ftq <timing>: delete flush condition for prefetch.req

ftq: add redirect sram size println

bpu: read oldest bits one stage ahead

ftq: cut redirect path from toIfuReq.valid

ftq: get missing perf counters back

tage_sc: use seperate wrbypass for each branch slot and use more entries for wrbypass in SC

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predict

ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

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Merge branch 'fix-oversize-not-corrected' into bpu-timing

Merge remote-tracking branch 'origin/master' into bpu-timing

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be oc

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

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IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still b

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

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ftq: remove false hit assertions

fix merge compile error

Merge branch 'bpu-timing' into fix-fdp-config

Merge remote-tracking branch 'origin/master' into bpu-timing

IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data s

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

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csr: optimize exception and trapTarget timing (#1372)

ubtb: use folded history class instead of seperately managing a ghr

ubtb: refactor prediction mechanism(temp commit)

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

core: delay csrCtrl for two cycles (#1336)

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits

core: delay csrCtrl for two cycles (#1336)

This commit adds DelayN(2) to some CSR-related signals, including
control bits to ITLB, DTLB, PTW, etc.

To avoid accessing the ITLB before control bits change, we also need
to delay the flush for two cycles. We assume branch misprediction or
memory violation does not cause csrCtrl to change.

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core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).