IFU <opt>: delete oversize logic

Frontend <timing>: add additional PMP checker

IFU <timing>: f2_data select signal optimization

Merge pull request #1428 from OpenXiangShan/ftq-timing

add one cycle on ifu/backend redirect

IFU <bug-fix>: raise page-fault when crossPage (#1421)

Merge branch 'bpu-timing-2' into frontend-final

IFU <bug-fix>: add f1_valid for from_bpu_f1_flush

ICache <timing>: separate Code and Data

IFU: <timing> f0_flush only flush control registers

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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Merge remote-tracking branch 'origin/master' into bpu-timing

IPrefetch: add prefetch address merge and counter (#1404)

* fix performance counter in ICacheMainpipe

* IPrefetch: add prefetch address merge and counter

IFU: fix fetching RVC instructions from mmio space bug (#1407)

* IFU: fix mmio RVC bug

* IFU: add resend address check for mmio

When a mmio fetch an RVI instruction which cross 64 bits,
IFU

IFU: fix fetching RVC instructions from mmio space bug (#1407)

* IFU: fix mmio RVC bug

* IFU: add resend address check for mmio

When a mmio fetch an RVI instruction which cross 64 bits,
IFU must send paddr + 2.U to fetch the higher 16 bits.
But the paddr + 2.U is not checked by TLB or PMP. This may cause
some unexpected fetch stuck problem.

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Merge remote-tracking branch 'origin/master' into bpu-timing

ICache: raise AF exception when parity wrong or L2 send corrupt (#1376)

* ICache: raise access fault when L2 send corrupt

* ICache: add ECC error connection

* chores: add comments and code cle

ICache: raise AF exception when parity wrong or L2 send corrupt (#1376)

* ICache: raise access fault when L2 send corrupt

* ICache: add ECC error connection

* chores: add comments and code clean-up

* ICache: raise AF when Meta/Data Parity wrong

* Update Frontend.scala

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ubtb: refactor prediction mechanism(temp commit)

Fix false hit bug after IFU timing optimization (#1367)

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit

Fix false hit bug after IFU timing optimization (#1367)

* fix invalidTakenFault use wrong seqTarget

* IFU: fix oversize bug

* ctrl: mark all flushes as level.flush for frontend

This commit changes how flushes behave for frontend.

When ROB commits an instruction with a flush, we notify the frontend
of the flush without the commit.

Flushes to frontend may be delayed by some cycles and commit before
flush causes errors. Thus, we make all flush reasons to behave the
same as exceptions for frontend, that is, RedirectLevel.flush.

* IFU: exclude lastTaken situation when judging beyond fetch

Co-authored-by: Yinan Xu <[email protected]>

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Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

FetchRequestBundle: signal rename

- target -> nextStartAddr
- nextlineStart = cachelineAlign(startAddr) + 64

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

IFU: delete fallThrough address

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfi

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

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core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

bpu: remove stage 3

update f2_mmio update logic (#1325)