1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.RVCDecoder 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import xiangshan.frontend.icache._ 26import utils._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28 29trait HasInstrMMIOConst extends HasXSParameter with HasIFUConst{ 30 def mmioBusWidth = 64 31 def mmioBusBytes = mmioBusWidth / 8 32 def maxInstrLen = 32 33} 34 35trait HasIFUConst extends HasXSParameter{ 36 def addrAlign(addr: UInt, bytes: Int, highest: Int): UInt = Cat(addr(highest-1, log2Ceil(bytes)), 0.U(log2Ceil(bytes).W)) 37 def fetchQueueSize = 2 38 39 def getBasicBlockIdx( pc: UInt, start: UInt ): UInt = { 40 val byteOffset = pc - start 41 (byteOffset - instBytes.U)(log2Ceil(PredictWidth),instOffsetBits) 42 } 43} 44 45class IfuToFtqIO(implicit p:Parameters) extends XSBundle { 46 val pdWb = Valid(new PredecodeWritebackBundle) 47} 48 49class FtqInterface(implicit p: Parameters) extends XSBundle { 50 val fromFtq = Flipped(new FtqToIfuIO) 51 val toFtq = new IfuToFtqIO 52} 53 54class UncacheInterface(implicit p: Parameters) extends XSBundle { 55 val fromUncache = Flipped(DecoupledIO(new InsUncacheResp)) 56 val toUncache = DecoupledIO( new InsUncacheReq ) 57} 58class NewIFUIO(implicit p: Parameters) extends XSBundle { 59 val ftqInter = new FtqInterface 60 val icacheInter = Vec(2, Flipped(new ICacheMainPipeBundle)) 61 val icacheStop = Output(Bool()) 62 val icachePerfInfo = Input(new ICachePerfInfo) 63 val toIbuffer = Decoupled(new FetchToIBuffer) 64 val uncacheInter = new UncacheInterface 65 val frontendTrigger = Flipped(new FrontendTdataDistributeIO) 66 val csrTriggerEnable = Input(Vec(4, Bool())) 67 val rob_commits = Flipped(Vec(CommitWidth, Valid(new RobCommitInfo))) 68 val iTLBInter = new BlockTlbRequestIO 69 val pmp = new ICachePMPBundle 70} 71 72// record the situation in which fallThruAddr falls into 73// the middle of an RVI inst 74class LastHalfInfo(implicit p: Parameters) extends XSBundle { 75 val valid = Bool() 76 val middlePC = UInt(VAddrBits.W) 77 def matchThisBlock(startAddr: UInt) = valid && middlePC === startAddr 78} 79 80class IfuToPreDecode(implicit p: Parameters) extends XSBundle { 81 val data = if(HasCExtension) Vec(PredictWidth + 1, UInt(16.W)) else Vec(PredictWidth, UInt(32.W)) 82 val frontendTrigger = new FrontendTdataDistributeIO 83 val csrTriggerEnable = Vec(4, Bool()) 84 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 85} 86 87 88class IfuToPredChecker(implicit p: Parameters) extends XSBundle { 89 val ftqOffset = Valid(UInt(log2Ceil(PredictWidth).W)) 90 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 91 val target = UInt(VAddrBits.W) 92 val instrRange = Vec(PredictWidth, Bool()) 93 val instrValid = Vec(PredictWidth, Bool()) 94 val pds = Vec(PredictWidth, new PreDecodeInfo) 95 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 96} 97 98class NewIFU(implicit p: Parameters) extends XSModule 99 with HasICacheParameters 100 with HasIFUConst 101 with HasPdConst 102 with HasCircularQueuePtrHelper 103 with HasPerfEvents 104{ 105 val io = IO(new NewIFUIO) 106 val (toFtq, fromFtq) = (io.ftqInter.toFtq, io.ftqInter.fromFtq) 107 val (toICache, fromICache) = (VecInit(io.icacheInter.map(_.req)), VecInit(io.icacheInter.map(_.resp))) 108 val (toUncache, fromUncache) = (io.uncacheInter.toUncache , io.uncacheInter.fromUncache) 109 110 def isCrossLineReq(start: UInt, end: UInt): Bool = start(blockOffBits) ^ end(blockOffBits) 111 112 def isLastInCacheline(addr: UInt): Bool = addr(blockOffBits - 1, 1) === 0.U 113 114 class TlbExept(implicit p: Parameters) extends XSBundle{ 115 val pageFault = Bool() 116 val accessFault = Bool() 117 val mmio = Bool() 118 } 119 120 val preDecoder = Module(new PreDecode) 121 val predChecker = Module(new PredChecker) 122 val frontendTrigger = Module(new FrontendTrigger) 123 val (preDecoderIn, preDecoderOut) = (preDecoder.io.in, preDecoder.io.out) 124 val (checkerIn, checkerOut) = (predChecker.io.in, predChecker.io.out) 125 126 io.iTLBInter.resp.ready := true.B 127 128 /** 129 ****************************************************************************** 130 * IFU Stage 0 131 * - send cacheline fetch request to ICacheMainPipe 132 ****************************************************************************** 133 */ 134 135 val f0_valid = fromFtq.req.valid 136 val f0_ftq_req = fromFtq.req.bits 137 val f0_doubleLine = fromFtq.req.bits.crossCacheline 138 val f0_vSetIdx = VecInit(get_idx((f0_ftq_req.startAddr)), get_idx(f0_ftq_req.nextlineStart)) 139 val f0_fire = fromFtq.req.fire() 140 141 val f0_flush, f1_flush, f2_flush, f3_flush = WireInit(false.B) 142 val from_bpu_f0_flush, from_bpu_f1_flush, from_bpu_f2_flush, from_bpu_f3_flush = WireInit(false.B) 143 144 from_bpu_f0_flush := fromFtq.flushFromBpu.shouldFlushByStage2(f0_ftq_req.ftqIdx) || 145 fromFtq.flushFromBpu.shouldFlushByStage3(f0_ftq_req.ftqIdx) 146 147 val wb_redirect , mmio_redirect, backend_redirect= WireInit(false.B) 148 val f3_wb_not_flush = WireInit(false.B) 149 150 backend_redirect := fromFtq.redirect.valid 151 f3_flush := backend_redirect || (wb_redirect && !f3_wb_not_flush) 152 f2_flush := backend_redirect || mmio_redirect || wb_redirect 153 f1_flush := f2_flush || from_bpu_f1_flush 154 f0_flush := f1_flush || from_bpu_f0_flush 155 156 val f1_ready, f2_ready, f3_ready = WireInit(false.B) 157 158 fromFtq.req.ready := toICache(0).ready && toICache(1).ready && f2_ready && GTimer() > 500.U 159 160 toICache(0).valid := fromFtq.req.valid //&& !f0_flush 161 toICache(0).bits.vaddr := fromFtq.req.bits.startAddr 162 toICache(1).valid := fromFtq.req.valid && f0_doubleLine //&& !f0_flush 163 toICache(1).bits.vaddr := fromFtq.req.bits.nextlineStart//fromFtq.req.bits.startAddr + (PredictWidth * 2).U //TODO: timing critical 164 165 /** <PERF> f0 fetch bubble */ 166 167 XSPerfAccumulate("fetch_bubble_ftq_not_valid", !f0_valid ) 168 XSPerfAccumulate("fetch_bubble_pipe_stall", f0_valid && toICache(0).ready && toICache(1).ready && !f1_ready ) 169 XSPerfAccumulate("fetch_bubble_sram_0_busy", f0_valid && !toICache(0).ready ) 170 XSPerfAccumulate("fetch_bubble_sram_1_busy", f0_valid && !toICache(1).ready ) 171 172 173 /** 174 ****************************************************************************** 175 * IFU Stage 1 176 * - calculate pc/half_pc/cut_ptr for every instruction 177 ****************************************************************************** 178 */ 179 180 val f1_valid = RegInit(false.B) 181 val f1_ftq_req = RegEnable(next = f0_ftq_req, enable=f0_fire) 182 // val f1_situation = RegEnable(next = f0_situation, enable=f0_fire) 183 val f1_doubleLine = RegEnable(next = f0_doubleLine, enable=f0_fire) 184 val f1_vSetIdx = RegEnable(next = f0_vSetIdx, enable=f0_fire) 185 val f1_fire = f1_valid && f1_ready 186 187 f1_ready := f2_ready || !f1_valid 188 189 from_bpu_f1_flush := fromFtq.flushFromBpu.shouldFlushByStage3(f1_ftq_req.ftqIdx) && f1_valid 190 // from_bpu_f1_flush := false.B 191 192 when(f1_flush) {f1_valid := false.B} 193 .elsewhen(f0_fire && !f0_flush) {f1_valid := true.B} 194 .elsewhen(f1_fire) {f1_valid := false.B} 195 196 val f1_pc = VecInit((0 until PredictWidth).map(i => f1_ftq_req.startAddr + (i * 2).U)) 197 val f1_half_snpc = VecInit((0 until PredictWidth).map(i => f1_ftq_req.startAddr + ((i+2) * 2).U)) 198 val f1_cut_ptr = if(HasCExtension) VecInit((0 until PredictWidth + 1).map(i => Cat(0.U(1.W), f1_ftq_req.startAddr(blockOffBits-1, 1)) + i.U )) 199 else VecInit((0 until PredictWidth).map(i => Cat(0.U(1.W), f1_ftq_req.startAddr(blockOffBits-1, 2)) + i.U )) 200 201 /** 202 ****************************************************************************** 203 * IFU Stage 2 204 * - icache response data (latched for pipeline stop) 205 * - generate exceprion bits for every instruciton (page fault/access fault/mmio) 206 * - generate predicted instruction range (1 means this instruciton is in this fetch packet) 207 * - cut data from cachlines to packet instruction code 208 * - instruction predecode and RVC expand 209 ****************************************************************************** 210 */ 211 212 val icacheRespAllValid = WireInit(false.B) 213 214 val f2_valid = RegInit(false.B) 215 val f2_ftq_req = RegEnable(next = f1_ftq_req, enable=f1_fire) 216 // val f2_situation = RegEnable(next = f1_situation, enable=f1_fire) 217 val f2_doubleLine = RegEnable(next = f1_doubleLine, enable=f1_fire) 218 val f2_vSetIdx = RegEnable(next = f1_vSetIdx, enable=f1_fire) 219 val f2_fire = f2_valid && f2_ready 220 221 f2_ready := f3_ready && icacheRespAllValid || !f2_valid 222 //TODO: addr compare may be timing critical 223 val f2_icache_all_resp_wire = fromICache(0).valid && (fromICache(0).bits.vaddr === f2_ftq_req.startAddr) && ((fromICache(1).valid && (fromICache(1).bits.vaddr === f2_ftq_req.nextlineStart)) || !f2_doubleLine) 224 val f2_icache_all_resp_reg = RegInit(false.B) 225 226 icacheRespAllValid := f2_icache_all_resp_reg || f2_icache_all_resp_wire 227 228 io.icacheStop := !f3_ready 229 230 when(f2_flush) {f2_icache_all_resp_reg := false.B} 231 .elsewhen(f2_valid && f2_icache_all_resp_wire && !f3_ready) {f2_icache_all_resp_reg := true.B} 232 .elsewhen(f2_fire && f2_icache_all_resp_reg) {f2_icache_all_resp_reg := false.B} 233 234 when(f2_flush) {f2_valid := false.B} 235 .elsewhen(f1_fire && !f1_flush) {f2_valid := true.B } 236 .elsewhen(f2_fire) {f2_valid := false.B} 237 238 // val f2_cache_response_data = ResultHoldBypass(valid = f2_icache_all_resp_wire, data = VecInit(fromICache.map(_.bits.readData))) 239 val f2_cache_response_data = VecInit(fromICache.map(_.bits.readData)) 240 241 242 val f2_except_pf = VecInit((0 until PortNumber).map(i => fromICache(i).bits.tlbExcp.pageFault)) 243 val f2_except_af = VecInit((0 until PortNumber).map(i => fromICache(i).bits.tlbExcp.accessFault)) 244 val f2_mmio = fromICache(0).bits.tlbExcp.mmio && !fromICache(0).bits.tlbExcp.accessFault && 245 !fromICache(0).bits.tlbExcp.pageFault 246 247 val f2_pc = RegEnable(next = f1_pc, enable = f1_fire) 248 val f2_half_snpc = RegEnable(next = f1_half_snpc, enable = f1_fire) 249 val f2_cut_ptr = RegEnable(next = f1_cut_ptr, enable = f1_fire) 250 251 val f2_resend_vaddr = RegEnable(next = f1_ftq_req.startAddr + 2.U, enable = f1_fire) 252 253 def isNextLine(pc: UInt, startAddr: UInt) = { 254 startAddr(blockOffBits) ^ pc(blockOffBits) 255 } 256 257 def isLastInLine(pc: UInt) = { 258 pc(blockOffBits - 1, 0) === "b111110".U 259 } 260 261 val f2_foldpc = VecInit(f2_pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth))) 262 val f2_jump_range = Fill(PredictWidth, !f2_ftq_req.ftqOffset.valid) | Fill(PredictWidth, 1.U(1.W)) >> ~f2_ftq_req.ftqOffset.bits 263 val f2_ftr_range = Fill(PredictWidth, f2_ftq_req.ftqOffset.valid) | Fill(PredictWidth, 1.U(1.W)) >> ~getBasicBlockIdx(f2_ftq_req.nextStartAddr, f2_ftq_req.startAddr) 264 val f2_instr_range = f2_jump_range & f2_ftr_range 265 val f2_pf_vec = VecInit((0 until PredictWidth).map(i => (!isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_except_pf(0) || isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_doubleLine && f2_except_pf(1)))) 266 val f2_af_vec = VecInit((0 until PredictWidth).map(i => (!isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_except_af(0) || isNextLine(f2_pc(i), f2_ftq_req.startAddr) && f2_doubleLine && f2_except_af(1)))) 267 268 val f2_paddrs = VecInit((0 until PortNumber).map(i => fromICache(i).bits.paddr)) 269 val f2_perf_info = io.icachePerfInfo 270 271 def cut(cacheline: UInt, cutPtr: Vec[UInt]) : Vec[UInt] ={ 272 if(HasCExtension){ 273 val result = Wire(Vec(PredictWidth + 1, UInt(16.W))) 274 val dataVec = cacheline.asTypeOf(Vec(blockBytes * 2/ 2, UInt(16.W))) 275 (0 until PredictWidth + 1).foreach( i => 276 result(i) := dataVec(cutPtr(i)) 277 ) 278 result 279 } else { 280 val result = Wire(Vec(PredictWidth, UInt(32.W)) ) 281 val dataVec = cacheline.asTypeOf(Vec(blockBytes * 2/ 4, UInt(32.W))) 282 (0 until PredictWidth).foreach( i => 283 result(i) := dataVec(cutPtr(i)) 284 ) 285 result 286 } 287 } 288 289 val f2_datas = VecInit((0 until PortNumber).map(i => f2_cache_response_data(i))) 290 val f2_cut_data = cut( Cat(f2_datas.map(cacheline => cacheline.asUInt ).reverse).asUInt, f2_cut_ptr ) 291 292 /** predecode (include RVC expander) */ 293 preDecoderIn.data := f2_cut_data 294 preDecoderIn.frontendTrigger := io.frontendTrigger 295 preDecoderIn.csrTriggerEnable := io.csrTriggerEnable 296 preDecoderIn.pc := f2_pc 297 298 val f2_expd_instr = preDecoderOut.expInstr 299 val f2_pd = preDecoderOut.pd 300 val f2_jump_offset = preDecoderOut.jumpOffset 301 val f2_hasHalfValid = preDecoderOut.hasHalfValid 302 val f2_crossPageFault = VecInit((0 until PredictWidth).map(i => isLastInLine(f2_pc(i)) && !f2_except_pf(0) && f2_doubleLine && f2_except_pf(1) && !f2_pd(i).isRVC )) 303 304 val predecodeOutValid = WireInit(false.B) 305 306 307 /** 308 ****************************************************************************** 309 * IFU Stage 3 310 * - handle MMIO instruciton 311 * -send request to Uncache fetch Unit 312 * -every packet include 1 MMIO instruction 313 * -MMIO instructions will stop fetch pipeline until commiting from RoB 314 * -flush to snpc (send ifu_redirect to Ftq) 315 * - Ibuffer enqueue 316 * - check predict result in Frontend (jalFault/retFault/notCFIFault/invalidTakenFault/targetFault) 317 * - handle last half RVI instruction 318 ****************************************************************************** 319 */ 320 321 val f3_valid = RegInit(false.B) 322 val f3_ftq_req = RegEnable(next = f2_ftq_req, enable=f2_fire) 323 // val f3_situation = RegEnable(next = f2_situation, enable=f2_fire) 324 val f3_doubleLine = RegEnable(next = f2_doubleLine, enable=f2_fire) 325 val f3_fire = io.toIbuffer.fire() 326 327 f3_ready := io.toIbuffer.ready || !f3_valid 328 329 val f3_cut_data = RegEnable(next = f2_cut_data, enable=f2_fire) 330 331 val f3_except_pf = RegEnable(next = f2_except_pf, enable = f2_fire) 332 val f3_except_af = RegEnable(next = f2_except_af, enable = f2_fire) 333 val f3_mmio = RegEnable(next = f2_mmio , enable = f2_fire) 334 335 val f3_expd_instr = RegEnable(next = f2_expd_instr, enable = f2_fire) 336 val f3_pd = RegEnable(next = f2_pd, enable = f2_fire) 337 val f3_jump_offset = RegEnable(next = f2_jump_offset, enable = f2_fire) 338 val f3_af_vec = RegEnable(next = f2_af_vec, enable = f2_fire) 339 val f3_pf_vec = RegEnable(next = f2_pf_vec , enable = f2_fire) 340 val f3_pc = RegEnable(next = f2_pc, enable = f2_fire) 341 val f3_half_snpc = RegEnable(next = f2_half_snpc, enable = f2_fire) 342 val f3_instr_range = RegEnable(next = f2_instr_range, enable = f2_fire) 343 val f3_foldpc = RegEnable(next = f2_foldpc, enable = f2_fire) 344 val f3_crossPageFault = RegEnable(next = f2_crossPageFault, enable = f2_fire) 345 val f3_hasHalfValid = RegEnable(next = f2_hasHalfValid, enable = f2_fire) 346 val f3_except = VecInit((0 until 2).map{i => f3_except_pf(i) || f3_except_af(i)}) 347 val f3_has_except = f3_valid && (f3_except_af.reduce(_||_) || f3_except_pf.reduce(_||_)) 348 val f3_pAddrs = RegEnable(next = f2_paddrs, enable = f2_fire) 349 val f3_resend_vaddr = RegEnable(next = f2_resend_vaddr, enable = f2_fire) 350 351 when(f3_valid && !f3_ftq_req.ftqOffset.valid){ 352 assert(f3_ftq_req.startAddr + 32.U >= f3_ftq_req.nextStartAddr , "More tha 32 Bytes fetch is not allowed!") 353 } 354 355 /*** MMIO State Machine***/ 356 val f3_mmio_data = Reg(Vec(2, UInt(16.W))) 357 val mmio_is_RVC = RegInit(false.B) 358 val mmio_resend_addr =RegInit(0.U(PAddrBits.W)) 359 val mmio_resend_af = RegInit(false.B) 360 361 val m_idle :: m_sendReq :: m_waitResp :: m_sendTLB :: m_tlbResp :: m_sendPMP :: m_resendReq :: m_waitResendResp :: m_waitCommit :: m_commited :: Nil = Enum(10) 362 val mmio_state = RegInit(m_idle) 363 364 val f3_req_is_mmio = f3_mmio && f3_valid 365 val mmio_commit = VecInit(io.rob_commits.map{commit => commit.valid && commit.bits.ftqIdx === f3_ftq_req.ftqIdx && commit.bits.ftqOffset === 0.U}).asUInt.orR 366 val f3_mmio_req_commit = f3_req_is_mmio && mmio_state === m_commited 367 368 val f3_mmio_to_commit = f3_req_is_mmio && mmio_state === m_waitCommit 369 val f3_mmio_to_commit_next = RegNext(f3_mmio_to_commit) 370 val f3_mmio_can_go = f3_mmio_to_commit && !f3_mmio_to_commit_next 371 372 val fromFtqRedirectReg = RegNext(fromFtq.redirect) 373 val f3_ftq_flush_self = fromFtqRedirectReg.valid && RedirectLevel.flushItself(fromFtqRedirectReg.bits.level) 374 val f3_ftq_flush_by_older = fromFtqRedirectReg.valid && isBefore(fromFtqRedirectReg.bits.ftqIdx, f3_ftq_req.ftqIdx) 375 376 val f3_need_not_flush = f3_req_is_mmio && fromFtqRedirectReg.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older 377 378 when(f3_flush && !f3_need_not_flush) {f3_valid := false.B} 379 .elsewhen(f2_fire && !f2_flush ) {f3_valid := true.B } 380 .elsewhen(io.toIbuffer.fire() && !f3_req_is_mmio) {f3_valid := false.B} 381 .elsewhen{f3_req_is_mmio && f3_mmio_req_commit} {f3_valid := false.B} 382 383 val f3_mmio_use_seq_pc = RegInit(false.B) 384 385 val (redirect_ftqIdx, redirect_ftqOffset) = (fromFtqRedirectReg.bits.ftqIdx,fromFtqRedirectReg.bits.ftqOffset) 386 val redirect_mmio_req = fromFtqRedirectReg.valid && redirect_ftqIdx === f3_ftq_req.ftqIdx && redirect_ftqOffset === 0.U 387 388 when(RegNext(f2_fire && !f2_flush) && f3_req_is_mmio) { f3_mmio_use_seq_pc := true.B } 389 .elsewhen(redirect_mmio_req) { f3_mmio_use_seq_pc := false.B } 390 391 f3_ready := Mux(f3_req_is_mmio, io.toIbuffer.ready && f3_mmio_req_commit || !f3_valid , io.toIbuffer.ready || !f3_valid) 392 393 // when(fromUncache.fire()) {f3_mmio_data := fromUncache.bits.data} 394 395 396 switch(mmio_state){ 397 is(m_idle){ 398 when(f3_req_is_mmio){ 399 mmio_state := m_sendReq 400 } 401 } 402 403 is(m_sendReq){ 404 mmio_state := Mux(toUncache.fire(), m_waitResp, m_sendReq ) 405 } 406 407 is(m_waitResp){ 408 when(fromUncache.fire()){ 409 val isRVC = fromUncache.bits.data(1,0) =/= 3.U 410 val needResend = !isRVC && f3_pAddrs(0)(2,1) === 3.U 411 mmio_state := Mux(needResend, m_sendTLB , m_waitCommit) 412 413 mmio_is_RVC := isRVC 414 f3_mmio_data(0) := fromUncache.bits.data(15,0) 415 f3_mmio_data(1) := fromUncache.bits.data(31,16) 416 } 417 } 418 419 is(m_sendTLB){ 420 mmio_state := m_tlbResp 421 } 422 423 is(m_tlbResp){ 424 mmio_state := m_sendPMP 425 mmio_resend_addr := io.iTLBInter.resp.bits.paddr 426 } 427 428 is(m_sendPMP){ 429 val pmpExcpAF = io.pmp.resp.instr 430 mmio_state := Mux(pmpExcpAF, m_waitCommit , m_resendReq) 431 mmio_resend_af := pmpExcpAF 432 } 433 434 is(m_resendReq){ 435 mmio_state := Mux(toUncache.fire(), m_waitResendResp, m_resendReq ) 436 } 437 438 is(m_waitResendResp){ 439 when(fromUncache.fire()){ 440 mmio_state := m_waitCommit 441 f3_mmio_data(1) := fromUncache.bits.data(15,0) 442 } 443 } 444 445 is(m_waitCommit){ 446 when(mmio_commit){ 447 mmio_state := m_commited 448 } 449 } 450 451 //normal mmio instruction 452 is(m_commited){ 453 mmio_state := m_idle 454 mmio_is_RVC := false.B 455 mmio_resend_addr := 0.U 456 } 457 } 458 459 //exception or flush by older branch prediction 460 when(f3_ftq_flush_self || f3_ftq_flush_by_older) { 461 mmio_state := m_idle 462 mmio_is_RVC := false.B 463 mmio_resend_addr := 0.U 464 mmio_resend_af := false.B 465 f3_mmio_data.map(_ := 0.U) 466 } 467 468 toUncache.valid := ((mmio_state === m_sendReq) || (mmio_state === m_resendReq)) && f3_req_is_mmio 469 toUncache.bits.addr := Mux((mmio_state === m_resendReq), mmio_resend_addr, f3_pAddrs(0)) 470 fromUncache.ready := true.B 471 472 io.iTLBInter.req.valid := (mmio_state === m_sendTLB) && f3_req_is_mmio 473 io.iTLBInter.req.bits.size := 3.U 474 io.iTLBInter.req.bits.vaddr := f3_resend_vaddr 475 io.iTLBInter.req.bits.debug.pc := f3_resend_vaddr 476 477 io.iTLBInter.req.bits.cmd := TlbCmd.exec 478 io.iTLBInter.req.bits.robIdx := DontCare 479 io.iTLBInter.req.bits.debug.isFirstIssue := DontCare 480 481 io.pmp.req.valid := (mmio_state === m_sendPMP) && f3_req_is_mmio 482 io.pmp.req.bits.addr := mmio_resend_addr 483 io.pmp.req.bits.size := 3.U 484 io.pmp.req.bits.cmd := TlbCmd.exec 485 486 val f3_lastHalf = RegInit(0.U.asTypeOf(new LastHalfInfo)) 487 488 val f3_predecode_range = VecInit(preDecoderOut.pd.map(inst => inst.valid)).asUInt 489 val f3_mmio_range = VecInit((0 until PredictWidth).map(i => if(i ==0) true.B else false.B)) 490 val f3_instr_valid = Wire(Vec(PredictWidth, Bool())) 491 492 /*** prediction result check ***/ 493 checkerIn.ftqOffset := f3_ftq_req.ftqOffset 494 checkerIn.jumpOffset := f3_jump_offset 495 checkerIn.target := f3_ftq_req.nextStartAddr 496 checkerIn.instrRange := f3_instr_range.asTypeOf(Vec(PredictWidth, Bool())) 497 checkerIn.instrValid := f3_instr_valid.asTypeOf(Vec(PredictWidth, Bool())) 498 checkerIn.pds := f3_pd 499 checkerIn.pc := f3_pc 500 501 /*** handle half RVI in the last 2 Bytes ***/ 502 503 def hasLastHalf(idx: UInt) = { 504 !f3_pd(idx).isRVC && checkerOut.fixedRange(idx) && f3_instr_valid(idx) && !checkerOut.fixedTaken(idx) && !checkerOut.fixedMissPred(idx) && ! f3_req_is_mmio 505 } 506 507 val f3_last_validIdx = ~ParallelPriorityEncoder(checkerOut.fixedRange.reverse) 508 509 val f3_hasLastHalf = hasLastHalf((PredictWidth - 1).U) 510 val f3_false_lastHalf = hasLastHalf(f3_last_validIdx) 511 val f3_false_snpc = f3_half_snpc(f3_last_validIdx) 512 513 val f3_lastHalf_mask = VecInit((0 until PredictWidth).map( i => if(i ==0) false.B else true.B )).asUInt() 514 515 when (f3_flush) { 516 f3_lastHalf.valid := false.B 517 }.elsewhen (f3_fire) { 518 f3_lastHalf.valid := f3_hasLastHalf 519 f3_lastHalf.middlePC := f3_ftq_req.nextStartAddr 520 } 521 522 f3_instr_valid := Mux(f3_lastHalf.valid,f3_hasHalfValid ,VecInit(f3_pd.map(inst => inst.valid))) 523 524 /*** frontend Trigger ***/ 525 frontendTrigger.io.pds := f3_pd 526 frontendTrigger.io.pc := f3_pc 527 frontendTrigger.io.data := f3_cut_data 528 529 frontendTrigger.io.frontendTrigger := io.frontendTrigger 530 frontendTrigger.io.csrTriggerEnable := io.csrTriggerEnable 531 532 val f3_triggered = frontendTrigger.io.triggered 533 534 /*** send to Ibuffer ***/ 535 536 io.toIbuffer.valid := f3_valid && (!f3_req_is_mmio || f3_mmio_can_go) && !f3_flush 537 io.toIbuffer.bits.instrs := f3_expd_instr 538 io.toIbuffer.bits.valid := f3_instr_valid.asUInt 539 io.toIbuffer.bits.enqEnable := checkerOut.fixedRange.asUInt & f3_instr_valid.asUInt 540 io.toIbuffer.bits.pd := f3_pd 541 io.toIbuffer.bits.ftqPtr := f3_ftq_req.ftqIdx 542 io.toIbuffer.bits.pc := f3_pc 543 io.toIbuffer.bits.ftqOffset.zipWithIndex.map{case(a, i) => a.bits := i.U; a.valid := checkerOut.fixedTaken(i) && !f3_req_is_mmio} 544 io.toIbuffer.bits.foldpc := f3_foldpc 545 io.toIbuffer.bits.ipf := VecInit(f3_pf_vec.zip(f3_crossPageFault).map{case (pf, crossPF) => pf || crossPF}) 546 io.toIbuffer.bits.acf := f3_af_vec 547 io.toIbuffer.bits.crossPageIPFFix := f3_crossPageFault 548 io.toIbuffer.bits.triggered := f3_triggered 549 550 val lastHalfMask = VecInit((0 until PredictWidth).map(i => if(i ==0) false.B else true.B)) 551 when(f3_lastHalf.valid){ 552 io.toIbuffer.bits.enqEnable := checkerOut.fixedRange.asUInt & f3_instr_valid.asUInt & lastHalfMask.asUInt 553 io.toIbuffer.bits.valid := f3_lastHalf_mask & f3_instr_valid.asUInt 554 } 555 556 /** external predecode for MMIO instruction */ 557 when(f3_req_is_mmio){ 558 val inst = Cat(f3_mmio_data(1), f3_mmio_data(0)) 559 val currentIsRVC = isRVC(inst) 560 561 val brType::isCall::isRet::Nil = brInfo(inst) 562 val jalOffset = jal_offset(inst, currentIsRVC) 563 val brOffset = br_offset(inst, currentIsRVC) 564 565 io.toIbuffer.bits.instrs (0) := new RVCDecoder(inst, XLEN).decode.bits 566 567 io.toIbuffer.bits.pd(0).valid := true.B 568 io.toIbuffer.bits.pd(0).isRVC := currentIsRVC 569 io.toIbuffer.bits.pd(0).brType := brType 570 io.toIbuffer.bits.pd(0).isCall := isCall 571 io.toIbuffer.bits.pd(0).isRet := isRet 572 573 io.toIbuffer.bits.acf(0) := mmio_resend_af 574 575 io.toIbuffer.bits.enqEnable := f3_mmio_range.asUInt 576 } 577 578 579 //Write back to Ftq 580 val f3_cache_fetch = f3_valid && !(f2_fire && !f2_flush) 581 val finishFetchMaskReg = RegNext(f3_cache_fetch) 582 583 val mmioFlushWb = Wire(Valid(new PredecodeWritebackBundle)) 584 val f3_mmio_missOffset = Wire(ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))) 585 f3_mmio_missOffset.valid := f3_req_is_mmio 586 f3_mmio_missOffset.bits := 0.U 587 588 mmioFlushWb.valid := (f3_req_is_mmio && mmio_state === m_waitCommit && RegNext(fromUncache.fire()) && f3_mmio_use_seq_pc) 589 mmioFlushWb.bits.pc := f3_pc 590 mmioFlushWb.bits.pd := f3_pd 591 mmioFlushWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := f3_mmio_range(i)} 592 mmioFlushWb.bits.ftqIdx := f3_ftq_req.ftqIdx 593 mmioFlushWb.bits.ftqOffset := f3_ftq_req.ftqOffset.bits 594 mmioFlushWb.bits.misOffset := f3_mmio_missOffset 595 mmioFlushWb.bits.cfiOffset := DontCare 596 mmioFlushWb.bits.target := Mux(mmio_is_RVC, f3_ftq_req.startAddr + 2.U , f3_ftq_req.startAddr + 4.U) 597 mmioFlushWb.bits.jalTarget := DontCare 598 mmioFlushWb.bits.instrRange := f3_mmio_range 599 600 mmio_redirect := (f3_req_is_mmio && mmio_state === m_waitCommit && RegNext(fromUncache.fire()) && f3_mmio_use_seq_pc) 601 602 /** 603 ****************************************************************************** 604 * IFU Write Back Stage 605 * - write back predecode information to Ftq to update 606 * - redirect if found fault prediction 607 * - redirect if has false hit last half (last PC is not start + 32 Bytes, but in the midle of an notCFI RVI instruction) 608 ****************************************************************************** 609 */ 610 611 val wb_valid = RegNext(RegNext(f2_fire && !f2_flush) && !f3_req_is_mmio && !f3_flush) 612 val wb_ftq_req = RegNext(f3_ftq_req) 613 614 val wb_check_result = RegNext(checkerOut) 615 val wb_instr_range = RegNext(io.toIbuffer.bits.enqEnable) 616 val wb_pc = RegNext(f3_pc) 617 val wb_pd = RegNext(f3_pd) 618 val wb_instr_valid = RegNext(f3_instr_valid) 619 620 /* false hit lastHalf */ 621 val wb_lastIdx = RegNext(f3_last_validIdx) 622 val wb_false_lastHalf = RegNext(f3_false_lastHalf) && wb_lastIdx =/= (PredictWidth - 1).U 623 val wb_false_target = RegNext(f3_false_snpc) 624 625 val wb_half_flush = wb_false_lastHalf 626 val wb_half_target = wb_false_target 627 628 /* false oversize */ 629 val lastIsRVC = wb_instr_range.asTypeOf(Vec(PredictWidth,Bool())).last && wb_pd.last.isRVC 630 val lastIsRVI = wb_instr_range.asTypeOf(Vec(PredictWidth,Bool()))(PredictWidth - 2) && !wb_pd(PredictWidth - 2).isRVC 631 val lastTaken = wb_check_result.fixedTaken.last 632 633 f3_wb_not_flush := wb_ftq_req.ftqIdx === f3_ftq_req.ftqIdx && f3_valid && wb_valid 634 635 val checkFlushWb = Wire(Valid(new PredecodeWritebackBundle)) 636 checkFlushWb.valid := wb_valid 637 checkFlushWb.bits.pc := wb_pc 638 checkFlushWb.bits.pd := wb_pd 639 checkFlushWb.bits.pd.zipWithIndex.map{case(instr,i) => instr.valid := wb_instr_valid(i)} 640 checkFlushWb.bits.ftqIdx := wb_ftq_req.ftqIdx 641 checkFlushWb.bits.ftqOffset := wb_ftq_req.ftqOffset.bits 642 checkFlushWb.bits.misOffset.valid := ParallelOR(wb_check_result.fixedMissPred) || wb_half_flush 643 checkFlushWb.bits.misOffset.bits := Mux(wb_half_flush, (PredictWidth - 1).U, ParallelPriorityEncoder(wb_check_result.fixedMissPred)) 644 checkFlushWb.bits.cfiOffset.valid := ParallelOR(wb_check_result.fixedTaken) 645 checkFlushWb.bits.cfiOffset.bits := ParallelPriorityEncoder(wb_check_result.fixedTaken) 646 checkFlushWb.bits.target := Mux(wb_half_flush, wb_half_target, wb_check_result.fixedTarget(ParallelPriorityEncoder(wb_check_result.fixedMissPred))) 647 checkFlushWb.bits.jalTarget := wb_check_result.fixedTarget(ParallelPriorityEncoder(VecInit(wb_pd.zip(wb_instr_valid).map{case (pd, v) => v && pd.isJal }))) 648 checkFlushWb.bits.instrRange := wb_instr_range.asTypeOf(Vec(PredictWidth, Bool())) 649 650 toFtq.pdWb := Mux(f3_req_is_mmio, mmioFlushWb, checkFlushWb) 651 652 wb_redirect := checkFlushWb.bits.misOffset.valid && wb_valid 653 654 655 /** performance counter */ 656 val f3_perf_info = RegEnable(next = f2_perf_info, enable = f2_fire) 657 val f3_req_0 = io.toIbuffer.fire() 658 val f3_req_1 = io.toIbuffer.fire() && f3_doubleLine 659 val f3_hit_0 = io.toIbuffer.fire() && f3_perf_info.bank_hit(0) 660 val f3_hit_1 = io.toIbuffer.fire() && f3_doubleLine & f3_perf_info.bank_hit(1) 661 val f3_hit = f3_perf_info.hit 662 val perfEvents = Seq( 663 ("frontendFlush ", wb_redirect ), 664 ("ifu_req ", io.toIbuffer.fire() ), 665 ("ifu_miss ", io.toIbuffer.fire() && !f3_perf_info.hit ), 666 ("ifu_req_cacheline_0 ", f3_req_0 ), 667 ("ifu_req_cacheline_1 ", f3_req_1 ), 668 ("ifu_req_cacheline_0_hit ", f3_hit_1 ), 669 ("ifu_req_cacheline_1_hit ", f3_hit_1 ), 670 ("only_0_hit ", f3_perf_info.only_0_hit && io.toIbuffer.fire() ), 671 ("only_0_miss ", f3_perf_info.only_0_miss && io.toIbuffer.fire() ), 672 ("hit_0_hit_1 ", f3_perf_info.hit_0_hit_1 && io.toIbuffer.fire() ), 673 ("hit_0_miss_1 ", f3_perf_info.hit_0_miss_1 && io.toIbuffer.fire() ), 674 ("miss_0_hit_1 ", f3_perf_info.miss_0_hit_1 && io.toIbuffer.fire() ), 675 ("miss_0_miss_1 ", f3_perf_info.miss_0_miss_1 && io.toIbuffer.fire() ), 676 // ("cross_line_block ", io.toIbuffer.fire() && f3_situation(0) ), 677 // ("fall_through_is_cacheline_end", io.toIbuffer.fire() && f3_situation(1) ), 678 ) 679 generatePerfEvent() 680 681 XSPerfAccumulate("ifu_req", io.toIbuffer.fire() ) 682 XSPerfAccumulate("ifu_miss", io.toIbuffer.fire() && !f3_hit ) 683 XSPerfAccumulate("ifu_req_cacheline_0", f3_req_0 ) 684 XSPerfAccumulate("ifu_req_cacheline_1", f3_req_1 ) 685 XSPerfAccumulate("ifu_req_cacheline_0_hit", f3_hit_0 ) 686 XSPerfAccumulate("ifu_req_cacheline_1_hit", f3_hit_1 ) 687 XSPerfAccumulate("frontendFlush", wb_redirect ) 688 XSPerfAccumulate("only_0_hit", f3_perf_info.only_0_hit && io.toIbuffer.fire() ) 689 XSPerfAccumulate("only_0_miss", f3_perf_info.only_0_miss && io.toIbuffer.fire() ) 690 XSPerfAccumulate("hit_0_hit_1", f3_perf_info.hit_0_hit_1 && io.toIbuffer.fire() ) 691 XSPerfAccumulate("hit_0_miss_1", f3_perf_info.hit_0_miss_1 && io.toIbuffer.fire() ) 692 XSPerfAccumulate("miss_0_hit_1", f3_perf_info.miss_0_hit_1 && io.toIbuffer.fire() ) 693 XSPerfAccumulate("miss_0_miss_1", f3_perf_info.miss_0_miss_1 && io.toIbuffer.fire() ) 694 XSPerfAccumulate("hit_0_except_1", f3_perf_info.hit_0_except_1 && io.toIbuffer.fire() ) 695 XSPerfAccumulate("miss_0_except_1", f3_perf_info.miss_0_except_1 && io.toIbuffer.fire() ) 696 XSPerfAccumulate("except_0", f3_perf_info.except_0 && io.toIbuffer.fire() ) 697} 698