ubtb: split the selection logic of validArray

and improve parameterizaton of fromMicroBTBEntry

Bump chisel to 3.5.0

parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, suppor

parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, support hist lengths that are not power of 2

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ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

bpu,ftq: remove oversize logic

bpu: read oldest bits one stage ahead

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predict

ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

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Merge remote-tracking branch 'origin/master' into bpu-timing

bpu: fix fallThruAddr on fallThruError, implement ghist diff mechanism

pred: use a same Mux1H both for hit and not hit conditions

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data s

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

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ubtb: use folded history class instead of seperately managing a ghr

ubtb: refactor prediction mechanism(temp commit)

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

FetchRequestBundle: signal rename

- target -> nextStartAddr
- nextlineStart = cachelineAlign(startAddr) + 64

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

IFU: delete fallThrough address

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

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Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfi

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

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bpu: remove stage 3

bpu: timing optimizations

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it

bpu: timing optimizations

* let the hit signal of each stage be used at last

Merge remote-tracking branch 'origin/master' into bpu-timing

bpu: timing optimizations

* use one hot muxes for ftb read resp
* generate branch history shift one hot vec for history update src sel
and update for all possible shift values