| #
cb4f77ce |
| 31-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: timing optimizations
* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le
bpu: timing optimizations
* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix
show more ...
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| #
d2568e58 |
| 23-Dec-2021 |
Lingrui98 <[email protected]> |
ftb: fix commit hit/miss perf counters
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| #
4c731adf |
| 23-Dec-2021 |
Lingrui98 <[email protected]> |
ftb: fix performance counters
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| #
b37e4b45 |
| 16-Dec-2021 |
Lingrui98 <[email protected]> |
ubtb: refactor prediction mechanism(temp commit)
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| #
c49b0e7f |
| 14-Dec-2021 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor
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| #
b30c10d6 |
| 14-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: timing optimizations
* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo
bpu: timing optimizations
* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment
show more ...
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| #
1ca0e4f3 |
| 10-Dec-2021 |
Yinan Xu <[email protected]> |
core: refactor hardware performance counters (#1335)
This commit optimizes the coding style and timing for hardware
performance counters.
By default, performance counters are RegNext(RegNext(_)).
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| #
3e52bed1 |
| 08-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: remove stage 3
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| #
82dc6ff8 |
| 07-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: parameter modification to reduce area
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| #
1bc6e9c8 |
| 02-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: remove unuseful 'pred_cycle' signal in meta SRAM
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| #
ab890bfe |
| 26-Nov-2021 |
Lingrui98 <[email protected]> |
bpu: timing optimizations
* use one hot muxes for ftb read resp
* generate branch history shift one hot vec for history update src sel
and update for all possible shift values
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| #
1ccea249 |
| 25-Nov-2021 |
Lingrui98 <[email protected]> |
bpu: timing optimizations
* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMux
bpu: timing optimizations
* decouple fall through address calculating logic from the pftAddr interface
* let ghr update from s1 has the highest priority
* fix the physical priority of PhyPriorityMuxGenerator
show more ...
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| #
efe3f3bb |
| 23-Oct-2021 |
Steve Gou <[email protected]> |
Merge branch 'master' into ftb-tail-shared
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| #
cd365d4c |
| 23-Oct-2021 |
rvcoresjw <[email protected]> |
add performance counters at core and hauncun (#1156)
* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable
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| #
9fdca42e |
| 22-Oct-2021 |
Lingrui98 <[email protected]> |
Merge branch 'master' into decoupled-frontend
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| #
1c8d9e26 |
| 20-Oct-2021 |
zoujr <[email protected]> |
BPU: Fix bug that update read override predict read result
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| #
5371700e |
| 17-Oct-2021 |
zoujr <[email protected]> |
BPU: Fix FTB Replacement bug
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| #
eeb5ff92 |
| 15-Oct-2021 |
Lingrui98 <[email protected]> |
frontend: let br/jmp share the last slot of an ftb entry, ghist update timing optimization
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| #
c6bf0bff |
| 15-Oct-2021 |
zoujr <[email protected]> |
BPU: Modify FTB to update each 2 cycles
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| #
bf358e08 |
| 14-Oct-2021 |
Lingrui98 <[email protected]> |
frontendBundle: add chiselName annotation for bundles, code clean ups and timing optimization (hopefully)
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| #
bb09c7fe |
| 14-Oct-2021 |
zoujr <[email protected]> |
BPU: Fix bug that FTB multiple hit
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| #
ac3f6f25 |
| 16-Sep-2021 |
zoujr <[email protected]> |
BPU: Modify FTB replacement strategy to plru
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| #
7f36ad77 |
| 10-Sep-2021 |
zoujr <[email protected]> |
BPU: Fix bug that false hit in coremark 10
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| #
ba4cf515 |
| 03-Sep-2021 |
Lingrui98 <[email protected]> |
parameters: ras size 32, btb size 4096
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| #
09c6f1dd |
| 01-Sep-2021 |
Lingrui98 <[email protected]> |
frontend: code clean ups
|