| #
c3d62b63 |
| 28-Oct-2024 |
Easton Man <[email protected]> |
style(frontend): manually wrap some line (#3791)
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| #
cf7d6b7a |
| 25-Oct-2024 |
Muzi <[email protected]> |
style(Frontend): use scalafmt formatting frontend (#3370)
Format frontend according to the scalafmt file drafted in #3061.
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| #
c4a59f19 |
| 27-Jun-2024 |
Yuandongliang <[email protected]> |
bpu: disable ittage when no indirect branch & ittage backward shift (#3092)
Co-authored-by: Easton Man <[email protected]>
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| #
fd3aa057 |
| 14-Jun-2024 |
Yuandongliang <[email protected]> |
FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997)
|
| #
74b57163 |
| 04-Nov-2023 |
Gao-Zeyu <[email protected]> |
ftq: reduce meta length (#2453)
MaxMetaLength: 256 -> 219
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
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| #
935edac4 |
| 21-Sep-2023 |
Tang Haojin <[email protected]> |
chore: remove deprecated brackets, APIs, etc. (#2321)
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| #
3c02ee8f |
| 25-Dec-2022 |
wakafa <[email protected]> |
Separate Utility submodule from XiangShan (#1861)
* misc: add utility submodule
* misc: adjust to new utility framework
* bump utility: revert resetgen
* bump huancun
|
| #
b60e4b0b |
| 26-Sep-2022 |
Lingrui98 <[email protected]> |
bpu: bypass uftb prediction directly to composer to avoid potential long wires
|
| #
c2d1ec7d |
| 16-Aug-2022 |
Lingrui98 <[email protected]> |
bpu: refactor prediction i/o bundles
|
| #
c4b44470 |
| 07-May-2022 |
Guokai Chen <[email protected]> |
pass reset vector from SimTop (#1545)
|
| #
6ee06c7a |
| 28-Feb-2022 |
Steve Gou <[email protected]> |
bpu: bring bpu control signals into use (#1477)
|
| #
85670bac |
| 09-Jan-2022 |
Lingrui98 <[email protected]> |
ras: should not push or pop when s3_redirect
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| #
ba246ba1 |
| 08-Jan-2022 |
Lingrui98 <[email protected]> |
composer: connect io.s3_fire to fix the problem of not recovering ras in s3
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| #
4813e060 |
| 07-Jan-2022 |
Lingrui98 <[email protected]> |
tage: improve performance and reduce area
* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre
tage: improve performance and reduce area
* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer
show more ...
|
| #
86d9c530 |
| 23-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: fix fallThruAddr on fallThruError, implement ghist diff mechanism
|
| #
b438d51d |
| 18-Dec-2021 |
Lingrui98 <[email protected]> |
ubtb: use folded history class instead of seperately managing a ghr
|
| #
b37e4b45 |
| 16-Dec-2021 |
Lingrui98 <[email protected]> |
ubtb: refactor prediction mechanism(temp commit)
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| #
c49b0e7f |
| 14-Dec-2021 |
Lingrui98 <[email protected]> |
Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor
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| #
1ca0e4f3 |
| 10-Dec-2021 |
Yinan Xu <[email protected]> |
core: refactor hardware performance counters (#1335)
This commit optimizes the coding style and timing for hardware
performance counters.
By default, performance counters are RegNext(RegNext(_)).
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| #
3e52bed1 |
| 08-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: remove stage 3
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| #
1bc6e9c8 |
| 02-Dec-2021 |
Lingrui98 <[email protected]> |
bpu: remove unuseful 'pred_cycle' signal in meta SRAM
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| #
e69b7315 |
| 12-Nov-2021 |
Lingrui98 <[email protected]> |
bpu: code clean ups, remove previous ghr impl
|
| #
dd6c0695 |
| 12-Nov-2021 |
Lingrui98 <[email protected]> |
bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top
|
| #
efe3f3bb |
| 23-Oct-2021 |
Steve Gou <[email protected]> |
Merge branch 'master' into ftb-tail-shared
|